This patch adds GPID, a helper method to look up GPIO community ID for
an index.
This patch also includes Intel's common GPIO ASL code. CGPM method in
the common code uses the GPID method introduced in this patch.
BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Id6a00fb8adef0285d6bbc35cd5a44539bd3be6b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40478
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables the use of AMD common block SATA driver for
Picasso. Since the common driver provides ACPI device name and PCI
device for SATA in SSDT, these are removed from picasso chip.c and
sb_pci0_fch.asl.
BUG=b:153858769
TEST=Verified that "STCR" device is correctly reported on trembyle in
SSDT.
Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support in common block SATA driver to add a PCI
device for SATA in SSDT and removes the SATA device from DSDT.
This makes it easier to ensure that we don't accidentally
make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and
scope.
BUG=b:153858769
Change-Id: I16ac36d997496ff33c5b44ec9bd2731b2b8799eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40769
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds .acpi_name() callback to SATA driver that returns
"STCR" as the ACPI device name for SATA. Since this is now done by the
common SATA driver, this change also removes the SATA device name
returned by stoneyridge in chip.c.
BUG=b:153858769
Change-Id: I5e0998be3016febbb3b0e91940750a38edb6a9e7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40768
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
sata.c was being added to ramstage based on the selection of
CONFIG_SOC_AMD_COMMON_BLOCK_HDA which is not correct. This change
fixes the error by including sata.c based on selection of
CONFIG_SOC_AMD_COMMON_BLOCK_SATA.
BUG=b:153858769
Change-Id: I5d23e5817872ddbb3d8d4f7dcabbaafcee4d51f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40766
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implements mainboard_get_dram_part_num() to override dram part number
with a part number read from CBI.
BUG=b:146464098
TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer, boot
and log into kernel, execute "mosys memory spd print id" and verify that
the memory part number from the cbi gets displayed properly.
Change-Id: I3a20691f601cb513ee0936c8d141233c3d06db3d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Pointer passed to print_spd_info() from meminit.c needs to be
dereferenced first, so this change dereferences it.
BUG=b:154352883
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, login to kernel and execute the following cbmem command:
localhost ~ # cbmem -c | grep LPDDR4X
and verify it returns "SPD: module type is LPDDR4X"
Change-Id: I5ff64121f0d50947c4946e9e02460dfb7319d01a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Since CB:40389, all platforms with CONFIG_VBOOT_EARLY_EC_SYNC need to
write back secdata in romstage. Those platforms currently all happen to
have CONFIG_VBOOT_SEPARATE_VERSTAGE set as well, but there's no official
dependency between those options. Change the Makefile to unconditionally
build the secdata access routines for romstage so that this would work
on other platforms as well.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0b3c79e9bb8af9d09ef91f5749953ca109dd2a40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
intel_igd_get_controller_info() does not need to modify the device
structure. Hence, this change makes the struct device * parameter to
intel_igd_get_controller_info() as const.
Change-Id: Ic044a80e3e2c45af6824a23f3cd0b08b94c0f279
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change makes the struct device * param to callback function
called by i2c_generic_fill_ssdt() as const. This is in preparation to
make struct device * param to fill_ssdt as const.
Change-Id: I7556b672a7b0172ded44747af394f5b32b6209aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40707
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
h8_has_bdc() and h8_has_wwan() do not need to modify the device
structure. Hence, this change makes the struct device * parameter to
these functions as const.
This is being done in preparation to make struct device * parameter to
fill_ssdt as const.
Change-Id: Id3d65d2de7b5161b0e7cff26055c00d5dae967dc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40706
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds uid parameter to drivers_ipmi_config that can be used
by ipmi_ssdt() to store the uid value to be used by
ipmi_write_acpi_tables. This allows to remove the requirement in
ipmi_ssdt() to update dev->command. This is being done in preparation
to make the struct device * parameter to fill_ssdt as const.
Change-Id: Ieb41771c75aae902191bba5d220796e6c343f8e0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40705
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
acpi_device_uid() and acpi_device_write_uid() do not need to make
changes to the device structure. Thus, this change marks struct
device * parameter to these functions as const.
Change-Id: I3755223766c78f93c57ac80caf392985cfd5c5e5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40702
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change:
1. Adds PCI device for graphics controller in ACPI SSDT tables using
acpi_device_write_pci_dev().
2. Gets rid of IGFX device from picasso acpi/northbridge.asl.
This makes it easier to ensure that we don't accidentally
make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and
scope.
BUG=b:153858769
Change-Id: I3a967cdc43b74f786e645d3fb666506070851a99
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change selects common block graphics driver for Picasso and also
adds PCI ID for Family 17h graphics controller to the graphics
driver.
Since the common driver provides .acpi_name() callback for graphics
device, soc_acpi_name() no longer needs to provide the ACPI name for
graphics device.
BUG=b:153858769
Change-Id: Id3ffcb05d8f8a253a0b27407d52d7907c507cabb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change adds a common graphics block device driver for AMD
SoCs. In follow-up CLs, this driver will be utilized for Picasso.
This driver is added to enable ACPI name and SSDT generation for
graphics controller.
BUG=b:153858769
Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change adds all the missing PCI device IDs for AMD Family
17h. IDs that were already present are updated to include _FAM17H_ in
the name instead of _PCO_ and _DALI_. This ensures that the PCI IDs
match the family and models as per the PPR. In cases where the
controller is present only on certain models, _MODEL##H_ is also
included in the name.
BUG=b:153858769
BRANCH=None
TEST=Verified that trembyle and dalboz still build.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia767d32ec22f5e58827e7531c0d3d3bac90d3425
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
IOMMU for AMD Family 17h Model 10-20h uses the same PCI device ID
0x15D1. This change updates the name to indicate that the PCI device
ID is supported for FP5(Model 18h) and FT5(Model 20h).
BUG=b:153858769
BRANCH=None
TEST=Trembyle and dalboz still build.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I17c782000ed525075a3e438ed820a22d9af61a26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This is missing configuration of Wiloc projects.
Following Wilco projects configuration. CB:32436
The power architecture on this platform is different than most of our
other x86 devices and needs some special handling to ensure it powers
up again after an EC reset.
BUG=b:150165131
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6da89de9401793a4e5c56a23c1018527819718cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40663
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, Deltaur’s I2C speed has not been tuned yet, so slow down
the H1 I2C to avoid I2C error for short term.
Error logs:
Reading cr50 TPM mode
I2C receive timeout
I2C read failed: bus 3 addr 0x50
BUG=b:154310066
TEST=Check H1 has no I2C error occurring and can be updated by gsctool.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD.
This commit provides _DSM method for driver to query driving strength.
TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4
BUG=b:154159888
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Populate SMBIOS type 17 tables using data from SPD and read via IOSF.
Refactor print_dram_info() to pass thru SPD data and channel/speed info.
Move call to print_dram_info() after cbmem initialization so the SMBIOS
data has somewhere to go.
Test: build/boot google/swanky, verify via dmidecode.
Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a FMAP which supports SMMSTORE and non-ChromeOS payloads,
since GeminiLake-based devices like Octopus cannot use an
automatically-generated FMAP due to strict layout requirements.
Change-Id: Iebacbea5b3a782b2abf1d6e28acd21b87dc9402b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40596
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Including i915.h just for the GMA/SSDT related functions means
dragging along all of i915_reg.h as well, which is problematic
since some platforms (like Apollo Lake) use overlapping symbols.
To avoid this conflict, break out the GMA/SSDT bits into their
own header which can be included without conflict.
Change-Id: I73fb7ef01abaafdcdbc44f1e3f5eb1883fc31616
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Allow to write protect only the WP_RO region in case of enabled VBOOT.
One can either lock the boot device in VERSTAGE early if VBOOT is enabled,
or late in RAMSTAGE. Both options have their downsides as explained below.
Lock early if you don't trust the code that's stored in the writeable
flash partition. This prevents write-protecting the MRC cache, which
is written in ramstage. In case the contents of the MRC cache are
corrupted this can lead to system instability or trigger unwanted code
flows inside the firmware.
Lock late if you trust the code that's stored in the writeable
flash partition. This allows write-protecting the MRC cache, but
if a vulnerability is found in the code of the writeable partition
an attacker might be able to overwrite the whole flash as it hasn't
been locked yet.
Change-Id: I72c3e1a0720514b9b85b0433944ab5fb7109b2a2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Introduce boot media protection settings and use the existing
boot_device_wp_region() function to apply settings on all
platforms that supports it yet.
Also remove the Intel southbridge code, which is now obsolete.
Every platform locks the SPIBAR in a different stage.
For align up with the common mrc cache driver and lock after it has been
written to.
Tested on Supermicro X11SSH-TF. The whole address space is write-protected.
Change-Id: Iceb3ecf0bde5cec562bc62d1d5c79da35305d183
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
