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28478 Commits

Author SHA1 Message Date
Arthur Heymans
6a8cde4927 soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE 
The cache as ram code will use one form of a non-eviction mode.

Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-04 16:20:28 +00:00
Joe Moore
a608dd80d5 vc/amd/agesa/[...]/Config: Avoid out-of-bounds warnings 
The memNTrainFlowControl array is generating Coverity warnings
in multiple places in code where it attempts to write to index 1.
The array is defined as either 2 elements or 1 of NULL depending
on #if (AGESA_ENTRY_INIT_POST == TRUE). This is likely a false
alarm from Coverity (memory should not be training outside of a
POST), but adding a second NULL element for the
AGESA_ENTRY_INIT_POST == FALSE case. Tested on Lenovo G505s.

Change-Id: Iaebe0830471e1854d6191c69cdaa552f900ba7a6
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1357451, 1357452, 1357453
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38176
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-04 16:09:09 +00:00
Joe Moore
a839581855 vc/amd/agesa: Delete mfParallelTraining.c 
Potential for out-of-bounds read. However, this code is not
used on F14, F15tn, or F16kb platforms. As can be seen in
vc/amd/agesa/f15tn/Config/PlatformInstall.h only multiple
socket F10 is supported. Tested on Lenovo G505s.

Change-Id: Ib71fe32d89840b9f25619d74980e562fd626952b
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241831
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-04 16:08:09 +00:00
Joe Moore
c156b584ee vc/amd/agesa: Fix uninitialized scalar variable 
AllocParams.Persist is used uninitialized when calling
HeapAllocateBuffer. This could lead to unpredictable or
unintended results. The f15tn and f16 versions of
AmdS3Save.c have already addressed this by initializing
AllocParams.Persist=0 in the same location in the code,
so adding to f14 only.

Change-Id: I2cbfbc4ad14a861e0cd92f130209b3b0f5b76a17
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
 2020-03-04 16:07:29 +00:00
Joe Moore
53e282acc0 vc/amd/agesa/f14/Proc/Mem: Fix uninitialized variable 
Uninitialized variable will contain an arbitrary value left from
earlier computations. This issue has already been addressed
in the f15tn and f16kb versions of this same file, so am
backporting the fix.

Change-Id: Id876107265689e08ad6760e514a4911f32b53da7
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38048
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-04 16:07:09 +00:00
Joe Moore
b753006f38 vc/amd/agesa/[...]/Proc/Mem: Delete unused function 
The generic MemNProgramNbPstateDependentRegistersUnb function is unused,
and generates a Coverity warning of an unused switch case. Only family
specific versions of this function are called elsewhere. Delete unused
function.

Change-Id: I2afc83861f4b3a13bfc1eef4920cd3023e608e94
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38493
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-04 16:06:47 +00:00
Prasun Gera
b5b5490bbd src/mainboard/lenovo/t530/Kconfig: Fix PCI device id for the iGPU 
Both T530 and W530 share the same PCI device id of 0166 for the iGPU.

Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a
Signed-off-by: Prasun Gera <prasun.gera@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-04 16:05:33 +00:00
Peter Lemenkov
9364afd3c0 mb/lenovo/t530/devicetree: Select docking_supported 
Looks like it should select it like any other Lenovo xx20/xx30 boards
around.

UNTESTED.

Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-04 16:03:31 +00:00
Peter Lemenkov
8d5c17389a mb/lenovo/t530/devicetree: Drop unnecessary initialization 
These two variables are initialized to zero by default.

Change-Id: I590f601b5297a9bfa93607442d7e0b8d79f1ab51
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-04 16:02:39 +00:00
Peter Lemenkov
c46dd39541 mb/lenovo/[tw]530/devicetree: Fix comment about chip codename 
Change-Id: I3323e713970041b0665ca17bbcad985cba600687
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-04 16:02:09 +00:00
Peter Lemenkov
257cc4f9c3 mb/lenovo/t530/*/*/devicetree: Align whitespace and comments across the boards 
Only whitespace changes, minor comments. This helps making diff between
devicetrees shorter.

Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-04 16:01:13 +00:00
Arthur Heymans
e7dd380402 nb/intel/nehalem: Use cache.h functions 
Some local functions need renaming to avoid name collision.

Change-Id: I0ca311c12f013e54e23ff0427421bfad0b747ea6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37195
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-04 15:58:19 +00:00
Elyes HAOUAS
761dbe228d nb/amd/agesa/family14/acpi: Fix comment 
"amdfam10" is no more.

Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38054
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-04 15:45:03 +00:00
Elyes HAOUAS
ee37c39a43 include/cpu/amd: Drop unused files 
Change-Id: Iff14250e52854d598967cfd3cbc98061be06e581
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38055
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-04 15:44:33 +00:00
Elyes HAOUAS
79ccc69332 src: capitalize 'PCIe' 
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-04 15:43:30 +00:00
Michael Niewöhner
f3161df2eb soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hidden 
The current elog implemetation searches for an active PME status bit by
iterating the PCI devices. On disabled or hidden devices a BUG gets
triggered: BUG: pch_log_rp_wake_source requests hidden ...

This is caused by the use of the PCH_DEV_* macros which resolve to
_PCH_DEV and finally call pcidev_path_on_root_debug.

Disabled devices are skipped already so we can safely use the DEVFNs
instead, circumventing the BUG.

Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
 2020-03-04 13:26:46 +00:00
Patrick Rudolph
573481bf6f cpu/intel/model_206ax: Lock MSR on all cores 
Lock MSR MSR_PKG_CST_CONFIG_CONTROL on all cores, not only the one
handling APM_CNT_FINALIZE.

Tested on HP Z220: FWTS no longer reports this as an issue.

Change-Id: I174d6c6c74fbba47992084cc44ebddf84eeeabd1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-03-04 10:39:39 +00:00
Nico Huber
63266c7e66 cpu/microcode: Fix config CPU_MICROCODE_CBFS_EXTERNAL_BINS 
Make the variable override for CPU_MICROCODE_CBFS_EXTERNAL_BINS local to
the target. Otherwise, `cpu_microcode_bin +=` lines that are evaluated
after `src/cpu/Makefile.inc` still append to it.

Change-Id: If81f307afc325ff3c1e987e9483ed5e45fdc403e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-04 10:38:55 +00:00
Srinidhi N Kaushik
4af0adb443 soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake 
update SerialIoUartAutoFlow settings for Tiger Lake platform.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-04 10:38:05 +00:00
Felix Singer
fdccfc6267 soc/intel/denverton_ns: Allow using FSP repo 
This commit is adding a dependency check for the FSP_USE_REPO
config option which so far was not able to deal with Denverton
systems.

Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
 2020-03-04 10:31:45 +00:00
Edward O'Callaghan
2d7bb7e141 src/ec,mainboard: Move weak smbios_system_sku() override inwards 
Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c
implementation and simply wrap a call to:
google_chromeec_smbios_system_sku().

BUG=b:150735116
BRANCH=none
TEST=none

Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-04 03:57:14 +00:00
Edward O'Callaghan
abd02cc1ca mainboard/google/dedede: Migrate onto SKU ID/fw_config helpers 
Leverage the common sku id space helper encoders.
dedede uses the non-legacy SKU ID space.

squash in,
  mainboard/google/dedede: Migrate onto get fw_config helper

BUG=b:149348474
BRANCH=none
TEST=only tested on hatch

Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-03-04 03:56:54 +00:00
Edward O'Callaghan
c6ab2ffaa0 mainboard/google/octopus: Migrate onto SKU ID helpers 
Leverage the common sku id space helper encoders and
set the sku id max to 0xff for legacy to ensure we
behave the same.

BUG=b:149348474
BRANCH=none
TEST=tested on hatch

Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-03-04 02:11:42 +00:00
Matt DeVillier
8187f11d1a sb/lynxpoint: hook up smmstore 
Adapted from implementation in sb/intel/common.

Test: build/boot variants of google/{beltino,slippy}
with Tianocore and SMMSTORE enabled

Change-Id: I64f520d17146206b8b9b41fc4f827539c5cfd507
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-03 14:18:01 +00:00
Maxim Polyakov
f0303dbf91 mb/asrock/h110m: Explain why some SATA ports are empty 
Change-Id: Ib0a24fab22ee082367b82b3e8ee7383f1f02a4ad
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-03 10:21:15 +00:00
Maxim Polyakov
7b98e3ebfc soc/intel/apl: disable NPK device in devicetree.cb 
Allows to enable/disable NPK device from the device tree:

    device pci 00.2 off end # NPK

Tested on Kontron come-mal10.

Change-Id: I910245d4ff35a6a0a9059fb6911d4426cdb999b6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38814
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-03 10:20:30 +00:00
Maxim Polyakov
3a02147d22 soc/intel/gpio_defs: add a new macro for pad config 
Adds PAD_CFG_NF_BUF_IOSSTATE_IOSTERM macro to configure native function,
iosstate, iosterm and disable input/output buffer. This is used in the
pad configurations for the Kontron COMe-mAL10 module board [1].

[1] https://review.coreboot.org/c/coreboot/+/39133

Change-Id: I7aa4d4dee34bd46a064079c576ed64525fd489e6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-03 10:20:12 +00:00
Srinidhi N Kaushik
9a768be0a5 vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake 
Update FSPM header to add Vtd related Upds for Tiger Lake platform
version 2457.

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
 2020-03-03 10:19:39 +00:00
Eric Lai
af681b62a0 mb/google/drallion: Enable cbfs SAR value 
Enable read SAR value from cbfs.

BUG=b:150347463
TEST=NA

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
 2020-03-03 10:19:16 +00:00
Wonkyu Kim
b3fa6a03a8 soc/intel/tigerlake: configure ethernet 
Configure ethernet based on board config

BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39153
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-03 10:18:17 +00:00
Angel Pons
d615230cce treewide: Replace BOARD_EMULATION_QEMU_X86 
It is equivalent to the CPU_QEMU_X86 symbol.

Change-Id: Ic16233e3d80bab62cc97fd075bdcca1780a6a2b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-03-03 10:16:09 +00:00
Angel Pons
632e241468 mb/emulation/Kconfig: Redefine BOARD_EMULATION_QEMU_X86 
Use CPU_QEMU_X86 as it is selected by both Qemu x86 mainboards.

Change-Id: I8d6bfbddeeb8f2c66c5ea7728a9919e7cda86e7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-03-03 10:15:35 +00:00
Angel Pons
7671bce33b mb/*/Kconfig: Factor out MAINBOARD_VENDOR 
Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.

Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-03-03 10:15:22 +00:00
Angel Pons
3e576739c9 mb/Kconfig: Align ROM size options 
Change-Id: I0160e72a8961f1aa34982f6348825708e7be9c40
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-03-03 10:13:31 +00:00
Matt DeVillier
3a7a3390f5 soc/broadwell: hook up smmstore 
Adapted from implementation in sb/intel/common.

Test: build/boot variants of google/{jecht, auron}
with Tianocore and SMMSTORE enabled

Change-Id: I4d2aaa80dad229a6c7b947d0edf8fb1174050ad0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-03 10:12:02 +00:00
Matt DeVillier
aa3b5e29f2 soc/braswell: hook up smmstore 
Adapted from implementation in sb/intel/common.

Test: build/boot variants of google/cyan with Tianocore
and SMMSTORE enabled

Change-Id: Ife4681983d0eecbc01c539b477664f3dd8bb9368
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-03 10:11:55 +00:00
Matt DeVillier
bd6bdc5c1d soc/baytrail: hook up smmstore 
Adapted from implementation in sb/intel/common.

Test: build/boot variants of google/rambi with Tianocore
and SMMSTORE enabled

Change-Id: Id8adeda982feba1cbcf5e04cf0bef0a6710ad4f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-03 10:11:42 +00:00
Angel Pons
73704533d6 LGA1155 mainboards: Remove gfx.did and gfx.ndid 
They are downright useless and result in ACPI errors. So, burn them.
Also, do a minor update to autoport's README about these values.

Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2020-03-03 10:11:02 +00:00
Ronak Kanabar
1c2313d339 soc/intel/tigerlake: Add Jasper lake GPIO support 
Add gpio definition for Jasper Lake gpio controller.

Also created a separate file for JSL and TGL gpio keeping common asl file.
gpio_soc_defs.h must pass correct information/macro values to asl file
for code to work.

GPIO controller includes 4 gpio community and 10 groups. Patch adds
definition for all gpio within community and groups

Updated IRQ mapping for all gpios

TEST=Check if jslrvp and tglrvp code is compiling

Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2020-03-03 10:09:26 +00:00
Arthur Heymans
8e9801380b Kconfig: Have GDB_STUB depend on DRIVERS_UART 
There is no reason to hide the GDB_STUB option when CONSOLE_SERIAL is
not set.

Change-Id: Icbf9a1ac0e617939cafa3d66774bbd467dc01cbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-03-03 07:45:23 +00:00
Keith Hui
2f3c37bd62 i82371eb: Roll 82093aa init into isa_init() 
This allows reuse of dev and reg32 already available,
and converting the block from #if to simple if.

Change-Id: I7a56f5a170986bbdf3c0c87eb5ead838ad55c659
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-03 07:43:08 +00:00
Keith Hui
2b9004de60 i82371eb: Drop support for older PIIX chips 
All boards using this code use i82371eb (that shares PCI ID with i82371ab).
Dropping the code lightens compressed ramstage by a few dozen bytes.

Change-Id: Iab1e83b8f5fff44a33619c7925e5448169a2a87c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38598
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-03 07:42:48 +00:00
Arthur Heymans
3fa3bf97e5 cpu/intel/slot_1: Cache romstage XIP execution 
Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37164
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-03 07:41:40 +00:00
Meera Ravindranath
872fced41d mb/google/dedede: Add memory initialization support for dedede 
Update memory parameters based on memory type supported by dedede
1. Update dq/dqs mappings
2. Update spd data for Micron Memory
3. Add SPD data binary files for supported memory types
4. Update other FSPM UPDs as part of memory initialization

BUG=none
BRANCH=none
TEST=Build dedede, flash and boot to kernel.

Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-03 07:41:12 +00:00
Keith Hui
ce62238998 sb/intel/i82371eb: Support reconfiguring GPO22/23 
XOE# and XDIR# can be used as GPOs 23/22 if X-Bus functionality is not
required. Turns out asus/p2b-ls is using them to control termination
for the onboard SCSI buses. Add support to allow this reconfiguration.

Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-03 07:36:53 +00:00
Keith Hui
7af59f709a sb/intel/i82371eb: Enable upper NVRAM bank 
Change-Id: I9ad127ca4394e27fc055ddf03012a195cb03bd94
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-03 07:35:13 +00:00
Meera Ravindranath
eaba79cc66 src/soc/tigerlake: Add memory configuration support for Jasper Lake 
BUG=none
BRANCH=none
TEST=Build and verify boot of WaddleDoo.

Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
 2020-03-03 04:07:39 +00:00
Wonkyu Kim
528ae9e811 soc/tigerlake: Correct FSP log interface 
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART.
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART

BUG=None
BRANCH=None
TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-02 23:43:12 +00:00
Felix Singer
23f870ad3a soc/intel/denverton/uart.c: Clean up code 
Since there is only one device ID used for UART,
an array is not needed. Therefore, just save the
device ID to the device variable.

Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-02 19:13:39 +00:00
Felix Singer
dbc90df35d soc/intel/denverton: Move PCI IDs to pci_ids.h 
This patch moves the PCI ID definitions to pci_ids.h file
and replaces every occurrence with the new names.

The resulting binary doesn't differ from the one
without this patch.

Used documents:
- Intel 337018

Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2020-03-02 19:13:10 +00:00