Duncan Laurie
3ed55e5da1
soc/intel/tigerlake: Remove eMMC/SD support
...
Tigerlake platform does not have built in eMMC/SD support so all
this code is unused and can be removed.
Change-Id: I70ff983d175375171d5a649378f32f1062c0876d
Signed-off-by: Duncan Laurie <dlaurie@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40372
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-17 20:00:15 +00:00
Duncan Laurie
1e06611768
soc/intel: Disable config option for SCS by default
...
The eMMC/SD interface is not present in all Intel platforms so this
change removes the default enable for the storage controller and
instead enables it in the specific SoCs that do provide it.
Currently this includes all platforms except Tigerlake.
Change-Id: I8b6cab41dbd5080f4a7801f01279f47e80ceaefd
Signed-off-by: Duncan Laurie <dlaurie@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-17 20:00:08 +00:00
Karthikeyan Ramasubramanian
a95907b066
ec/google/chromeec: Update the USBC ACPI device hierarchy
...
Type C connector class driver in kernel (v5.4) expects the Type C ACPI
device under ChromeEC ACPI device scope. Currently the Type C ACPI
device is populated under ChromeEC device's parent. This leads to
incorrect casting of Type C's parent device and hence a crash. Move the
Type C device under ChromeEC ACPI device.
BUG=b:153518804
TEST=Build and boot the mainboard. Ensure that the USBC ACPI device is
populated under ChromeEC ACPI device.
Scope (\_SB.PCI0.LPCB.EC0.CREC)
{
Device (USBC)
{
Name (_HID, "GOOG0014") // _HID: Hardware ID
...
}
}
Change-Id: I628489bc420d7a3db4ad3cb93d085d568c6de507
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-04-17 18:51:04 +00:00
Maxim Polyakov
b2634c1f98
intel/common: add a macro to set ownership for GPI
...
Adds a new macro that allow to set the DRIVER or ACPI as host software
ownership for the GPI pad using the parameter own. Thus, this macro can
define more variants for pad configuration than others.
This is necessary to describe in more detail the configuration for the
Tioga Pass OCP server [1] and other boards. In addition, these changes
will be used to automatically generate macros [2] and great simplify
this task.
[1] https://review.coreboot.org/c/coreboot/+/39427
[2] https://review.coreboot.org/c/coreboot/+/35643
Change-Id: I9c191fb6935e94da6e296f8fee0b91a973534e1a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-04-17 18:18:17 +00:00
Patrick Rudolph
afa71b6113
configs: Add qemu aarch64 target with FIT support
...
Add a defconfig which allows to place a large uImage/FIT payload
in it to boot test the binary on qemu-system-aarch64 using u-root
and kexec-tools.
Change-Id: I95ca187b68ff883152421bd7612b494cd63e8d02
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-04-17 15:33:18 +00:00
Rajat Jain
c049572385
ec/google/chromeec: Add host command EC_CMD_GET_KEYBD_CONFIG
...
Add command to query the EC for the keyboard layout. Also
add supporting data structures for the exchange.
Signed-off-by: Rajat Jain <rajatja@google.com >
Change-Id: I26aff6dd0e701e0cecb3b66bc54c5a23688f0109
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-04-17 01:07:25 +00:00
Marshall Dawson
74bee3c8ad
vc/amd/fsp/picasso: Add file for GUIDs
...
Begin a file for GUIDs used by the FSP.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: Ied5c5085ea8ed55439192be8a44fa401aeb559a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38697
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-16 23:42:57 +00:00
Felix Held
7d30418605
soc/amd/common/psp: refactor psp_print_cmd_status parameters
...
psp_print_cmd_status only needs data from the mbox buffer header and not
the whole buffer. This avoids type casts when the buffer type isn't
mbox_default_buffer.
BUG=b:153677737
Change-Id: I8688b66fefe89fc4f3ce2207d4360ceb2dbaef12
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40412
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-16 23:17:41 +00:00
Marshall Dawson
90b8339b8d
soc/amd/picasso: Notify PSP system is going to sleep state
...
BUG=b:153677737
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: Ic72bd5f5710181ca4f282feba5f7531b098c907a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40298
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-16 23:17:23 +00:00
Felix Held
43126edc3a
soc/amd/common/psp: Add notify_sx_info
...
Add the command to tell the PSP the system is going to a sleep
state.
BUG=b:153677737
Change-Id: I50da358e1f8438b46dbb1bda593becf6dd4549ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-on: https://chromium-review.googlesource.com/2020367
Reviewed-on: https://chromium-review.googlesource.com/2110764
Reviewed-on: https://chromium-review.googlesource.com/2121159
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2020-04-16 23:17:09 +00:00
Marshall Dawson
e8ffa9ffd3
soc/amd/psp: Add SmmInfo command
...
Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's
SMM configuration. Once the BootDone command is sent, the PSP only
responds to commands where the buffer is in SMM memory.
Set aside a region for the core-to-PSP command buffer and the
PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read
as non-zero during an SMI.
Add calls to soc functions for the soc to populate the trigger info and
register info (v2 only).
Add functions to set up the structures needed for the SmmInfo function
in Picasso support. Issue a SW SMI, and add a new handler to call the
new PSP function.
BUG=b:153677737
Change-Id: I10088a53e786db788740e4b388650641339dae75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2020-04-16 23:15:09 +00:00
BryantOu
e26da8ba16
intel/common/block/lpc: Add new device IDs for Lewisburg PCH
...
Add C621A, C627A and C629A SKU IDs. C621A is used in the Whitley Product.
We need to add device ID for setting LPC resources.
Refer to Intel C620 series PCH EDS (547817).
Change-Id: I19a4024808d5aa72a9e7bd434613b5e7c9284db8
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40395
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-16 18:42:57 +00:00
David Wu
ffe26b6c1a
mb/google/hatch/var/kindred: Override VBT selection for kled
...
Override VBT to fix CRC error issue with psr2 panel for kled.
Cq-Depend: chrome-internal:2877637
BUG=b:145963505
BRANCH=hatch
TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage
Change-Id: If201d449e910f80dc514c142aec4808a44fa31a9
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2020-04-16 18:40:14 +00:00
Angel Pons
77410efebf
MAINTAINERS: Update GA-H61M-S2PV
...
Commit 991ee05th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2020-04-16 17:02:28 +00:00
Angel Pons
0b9ed92c40
MAINTAINERS: Drop invalid paths
...
Remove references to directories that no longer exist.
Change-Id: Ief45bf4c00c6cbf9b5acef72a76c05a86a7ebedc
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2020-04-16 17:02:19 +00:00
Iru Cai
56360d4f7b
autoport: use GMA_STATIC_DISPLAYS
...
Change-Id: Ie988b2caeb2cdc07a3d6466b7ae3501df469ef41
Signed-off-by: Iru Cai <mytbk920423@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-16 10:15:21 +00:00
Iru Cai
b95a1a4ea0
autoport: Support bigger ACPI tables
...
DSDT can be bigger than 0x10000 bytes, so increase the space up to 1MB
for an ACPI table and support lines in acpidump.log with address
higher than 0x10000.
Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d
Signed-off-by: Iru Cai <mytbk920423@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31759
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-16 10:15:07 +00:00
Michał Żygowski
11278dbabe
SeaBIOS: fix threaded hardware initialization during oprom execution
...
Since SeaBIOS rel-1.7.5 CONFIG_THREAD_OPTIONROMS is not present in its
config. The threaded hardware initialization during optionrom execution
is now controlled with a CBFS file. Add appropriate integer to CBFS when
threaded hardware initialization is selected in coreboot's Kconfig.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Change-Id: I9b5a532b609c6addf31ccdb6be03ff2e937ad326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-16 09:03:59 +00:00
Aaron Durbin
53525771f0
ec/google/chromeec: add BOARD_VERSION CBI support
...
Obtaining the CBI_TAG_BOARD_VERSION value wasn't in the code base.
Add the binding for it so it can be used.
BUG=b:153640981
Change-Id: Ie2f289631f908014432596448e56b5048a196a10
Signed-off-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-04-16 03:53:31 +00:00
Tim Chen
e433bccb86
mb/google/puff: Add variant specific DPTF parameters
...
Modify DPTF parameters for OEM EVT build from thermal team.
BUG=b:153589525
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage and boot on puff board
Change-Id: I36db172e4d2ccc854856641c510cff9fe04ea235
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
2020-04-16 00:00:46 +00:00
Andrew McRae
b438dab367
mb/google/hatch: Add Kaisa variant
...
A verbatim copy of variants/puff
V.2: rebased on duffy.
BUG=b:152951180
BRANCH=none
TEST=none
Change-Id: I7ea28e96c8b6867e17097a8bfab848928195654d
Signed-off-by: Andrew McRae <amcrae@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Daniel Kurtz <djkurtz@google.com >
2020-04-15 23:34:29 +00:00
Edward O'Callaghan
3980132987
mb/google/hatch: Add Duffy variant
...
A verbatim copy of variants/puff.
BUG=b:152951181
BRANCH=none
TEST=none
Change-Id: I9ac262bba60a8d0059722e947ed1b47dddb94f55
Signed-off-by: Edward O'Callaghan <quasisec@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40223
Reviewed-by: Daniel Kurtz <djkurtz@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-15 23:34:21 +00:00
Nico Huber
df5b051e6d
mb/kontron/ktqm77: Extend SATA CMOS option with "legacy" mode
...
TEST=Booted Linux 2.6.12 w/o native Intel IDE driver and confirmed
working SATA drive.
Change-Id: I85f72a172bcbc4c8b4bfb7a2baed7c6739b2d9f8
Signed-off-by: Nico Huber <nico.huber@secunet.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-15 21:10:46 +00:00
Nico Huber
56473ca9a7
sb/intel/bd82x6x/sata: Clean up IDE modes
...
Don't set legacy timing values that don't affect the hardware but
enable the OOB retry mode as already done on the AHCI path.
Change-Id: I0b078d7790ca801a89066ef6a161d900be5eb778
Signed-off-by: Nico Huber <nico.huber@secunet.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-15 20:59:48 +00:00
T Michael Turney
14929253a5
trogdor: add support for Bubs variant
...
Change-Id: I4d9bc98863c4f33c19e295b642f48c51921ed984
Signed-off-by: T Michael Turney <mturney@codeaurora.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37069
Reviewed-by: Bob Moragues <moragues@google.com >
Reviewed-by: Julius Werner <jwerner@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-15 19:57:59 +00:00
Nico Huber
374d7c2e94
Do not select USE_BLOBS
...
The `USE_BLOBS` config only exists for idealistic reasons. If we would
allow us to use blobs by default, we wouldn't need that option and could
just always do it. It's generally debatable for the project as a whole,
but not per board/subject.
Change-Id: I8591862699aef02e5a4ede32655fc82c44c97555
Signed-off-by: Nico Huber <nico.huber@secunet.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-04-15 19:11:08 +00:00
Angel Pons
0b50099c8b
MAINTAINERS: Fix a comment
...
A space was missing before the asterisks.
Change-Id: I1cb62a9efc8e15c09cdebb49956f0edeb032beb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-04-15 15:32:19 +00:00
Angel Pons
68da241ba4
soc/intel/apl/report_platform.c: Fix typo
...
"Aplollolake" => "Apollolake"
Change-Id: I1881d40b5f71d07d5d217b4380241cc14467fb1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40407
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-15 15:04:19 +00:00
Ronak Kanabar
31fef3f6f8
mb/intel/jasperlake_rvp: Update JSLRVP USB configuration
...
Remove extra USB port entry because it came in from copy
patch from the previous board and configure USB over-current
pins as per JSLRVP.
Change-Id: If9df8e330d31ed81207dfdfa2ab96fd4d49f3f0c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39403
Reviewed-by: V Sowmya <v.sowmya@intel.com >
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-15 14:05:55 +00:00
Marshall Dawson
6d2a51eb85
cpu/x86/acpi: Add assignments to ACPI_Sn enums
...
Explicitly assign numerical values to the enumerated sleep state
values.
BUG=b:153854742
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: I1de2e7f65a2dc3f8a9a1c5fd83d164871a4a2b96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-15 14:05:28 +00:00
Nico Huber
63be06008d
sb/intel/bd82x6x/sata: Add legacy mode support
...
Legacy mode is supposed to help with IDE controller drivers that don't
know Intel's "native" IDE interface. We extend the `sata_mode` NVRAM
variable to provide the following choices:
* 0 "AHCI" - AHCI interface
* 1 "Compatible" - Intel's "native" interface
* 2 "Legacy" - Legacy interface
Change-Id: I0e7a4befa02772f620602fa2a92c3583895d4d1c
Signed-off-by: Nico Huber <nico.huber@secunet.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-15 14:03:27 +00:00
Michał Żygowski
9ff2af2b47
sb/intel/bd82x6x/lpc.c: configure CLKRUN_EN according to SKU
...
CLKRUN_EN bit available for mobile is reserved on desktop SKUs.
PSEUDO_CLKRUN_EN bit available for desktop is reserved for mobile SKUs.
Configure these bits accordign to SKU.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Change-Id: I5295eb2bec27c77f800cc2ade9093e97ede47789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-04-15 14:01:56 +00:00
Marshall Dawson
5a73fc35e2
soc/amd/picasso: Add common PSP support
...
Add a new psp.c file so the base address can be determined, and select
the common/block/psp feature.
BUG=b:153677737
Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-on: https://chromium-review.googlesource.com/2020368
Tested-by: Eric Peers <epeers@google.com >
Reviewed-by: Eric Peers <epeers@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-15 12:24:17 +00:00
Felix Held
0c70b4ac11
soc/amd/common/psp: add Kconfig description to interface version
...
BUG=b:153677737
Change-Id: I5b017dfc92563ec4f0a2edb24416d6b65587d9a3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-15 12:23:35 +00:00
Felix Held
1ad73926f2
soc/amd/common/block/psp: move psp_load_named_blob to psp_gen1.c
...
This function is only needed and valid for the 1st generation PSP
interface used on stoneyridge.
BUG=b:153677737
Change-Id: Ia1be09c32271fe9480a0acbe324c4a45d8620882
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-15 12:23:19 +00:00
Edward O'Callaghan
609b7fb303
mb/google/puff: Fix up WLAN_OFF gpio configuration
...
BUG=b:152927525
BRANCH=none
TEST=builds
Change-Id: I691377624c870eb0fc6f7e84a4b9cd50b7b09654
Signed-off-by: Edward O'Callaghan <quasisec@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Chen <tim-chen@quanta.corp-partner.google.com >
Reviewed-by: Daniel Kurtz <djkurtz@google.com >
2020-04-15 10:17:26 +00:00
Arthur Heymans
b894ad5233
mb/lenovo/x60: Add vboot support
...
It's relatively slow to boot. It takes 1.5s to get to the payload.
In timestamps there are entries related to TPM, which are somewhat
weird given that the TPM is not enabled on this device (buggy).
TESTED: boot X60, with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y you
can force the recovery bootpath.
Change-Id: Ia9666194e98b7d23b97eaff08e6177684e35eca7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-15 10:06:58 +00:00
Edward O'Callaghan
4f176913c1
mainboard/puff: Tune ALC5682I rise_fall times on i2c
...
Tunes the headphone amp i2c with measured signal shape.
BUG=b:147192377
BRANCH=none
TEST=builds and measured i2c frequency below 400khz
Change-Id: I60f73bcf60ed140f595c953be371b982a63f7b95
Signed-off-by: Edward O'Callaghan <quasisec@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
Reviewed-by: Daniel Kurtz <djkurtz@google.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2020-04-15 02:35:22 +00:00
Julius Werner
ef43711aad
trogdor: Add third RAM_CODE pin
...
We decided to add a third RAM_CODE pin to the Trogdor family for devices
after rev1. This patch adds support to read it. Since the newly used pin
was previously unconnected (not pulled down) on rev1, this will change
the RAM_CODE result for previous versions (and actually make it
undetermined until we enable tri-state). But since we're not actually
using RAM_CODE for anything yet, and since those are development
revisions that will eventually be discontinued, this should be fine.
Signed-off-by: Julius Werner <jwerner@chromium.org >
Change-Id: I9b52982f17646a305b1a3e2c7d37606a7c38d0c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Philip Chen <philipchen@google.com >
2020-04-14 21:32:57 +00:00
Seunghwan Kim
aee0baf069
mb/google/nightfury: Update tdp_pl1_override value
...
Update tdp_pl1_override value to 15W for CML-U based nightfury platform.
BUG=None
BRANCH=firmware-hatch-12672.B
TEST=Built
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com >
Change-Id: Ib0155b961b9d304bed2e9456c4964ebd598af4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2020-04-14 10:10:04 +00:00
John Zhao
17277ff658
soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
...
TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT.
Fix the scope type to be PCI_SUB.
BUG=b:141609884
TEST=Booted to kernel and verified no TBT PCIE root ports scope
type mismatch error in kernel log.
Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21
Signed-off-by: John Zhao <john.zhao@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-04-14 10:09:27 +00:00
Eric Lai
72d9366721
mb/google/deltaur: Enable Melfas touch screen for Deltan
...
Reference Drallion to add device tree for Melfas touch screen.
BUG=b:152924290
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-04-14 10:08:48 +00:00
Julia Tsai
9e0dd9af47
mb/google/octopus/variants/lick: Disable xHCI compliance mode
...
Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.
BRANCH=octopus
BUG=b:153782196
TEST=Verified usb operation successfully.
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com >
Change-Id: If0bf68c8cf0a2a3b857395b6b82e46cc384ba65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39874
Reviewed-by: Henry Sun <henrysun@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-14 10:08:37 +00:00
Dtrain Hsu
afc593d99c
mb/google/dedede: Enable ELAN touchscreen for Waddledoo
...
Add ELAN EKTH6918 USI touchscreen support.
BUG=b:152936745
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
Change-Id: I030c7d7e76a9705be06fe907c4ac279e247cb163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marco Chen <marcochen@google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2020-04-14 10:07:58 +00:00
Dtrain Hsu
3fe5f2cfa4
mb/google/dedede: Enable SIS touchscreen for Waddledoo
...
Add SiS9813 USI touchscreen support.
BUG=b:152936541
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
Change-Id: Id04c46c763fdf68418bf2e97be4c8bb6bb73c749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40250
Reviewed-by: Marco Chen <marcochen@google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-14 10:07:50 +00:00
Subrata Banik
53e82f67ea
mb/intel/{jasperlake_rvp, tglrvp}: Remove unused files
...
This patch removes unused "spd_util.c" files from mainboard
directory.
Change-Id: Ibd011be578fa256afb61796d5ceeea073e852fe9
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com >
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com >
2020-04-14 10:06:19 +00:00
Wonkyu Kim
3ba64ca3d1
soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN
...
BUG=b:151161585
BRANCH=none
TEST=build and boot ripto/volteer and check FSP logs for lockdown
parameters
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com >
Change-Id: I63cec8a718285f424914e426d0399ed821588dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-04-14 10:05:50 +00:00
Paul Menzel
aecbe7a988
mb/google/hatch: Use tabs for alignment
...
Change-Id: I38d429245810f64a03253b5076391af843f8d0de
Fixes: e2ac5b7a36pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-14 10:05:14 +00:00
Paul Menzel
71e2b2903a
mb/google/poppy/variants/nami: Use tabs for alignment
...
Change-Id: Ia707295c55ce2e18eb8970506be10b7b0f3fbc39
Fixes: b77cbbe1b0pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-04-14 10:05:02 +00:00
Paul Menzel
0fdd9fd2aa
mb/ocp/tiogapass: Add missing spaces around operators
...
Change-Id: I8930e96e5f2c45b8658dc4dfe1ab57d573e7b26f
Fixes: b75bcc978apmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com >
2020-04-14 10:04:35 +00:00
