sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
30,247 Commits 47 Branches 30 Tags
3647920722a1c6abc06be4d802efe835f0a7775e
Commit Graph

6 Commits

Author SHA1 Message Date
Elyes HAOUAS
276d46ac05 src: Add missing include <device/pci_ops.h> 
Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33526
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-07-12 17:10:56 +00:00
Elyes HAOUAS
20eaef024c src: Add missing include 'console.h' 
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2019-04-23 10:00:39 +00:00
Kyösti Mälkki
c70eed1e62 device: Use pcidev_on_root() 
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-01-06 01:17:54 +00:00
Lee Leahy
f74ce24de1 soc/intel/quark: Clean up debug output levels 
Change the debug output levels for quark:
*  Remove excess debug output
*  Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c

TEST=Build and run on Galileo Gen2

Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2016-08-05 01:55:17 +02:00
Lee Leahy
a6de5470fa soc/intel/quark: Initialize some of the FADT base registers 
Initialize the base addresses for:
*  Power management control
*  Power management status
*  Reset
*  Power management timer
*  General-Purpose Event 0

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   * CONFIG_PAYLOAD_ELF=y
   * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
*  Testing successful when:
   *  Register address are properly displayed by the payload
   *  "reset -c" performs a reset and reboots the system
   *  "reset -w" performs a reset and reboots the system
   *  "reset -s" performs a reset and turns off the power

Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13764
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
 2016-02-29 04:59:56 +01:00
Lee Leahy
d3de85cbcc soc/intel/quark: Add the initial pieces required for ACPI tables 
Enable ACPI tables
TEST=None

Change-Id: I38b90f54cd9b00b063557c08980e71851bf3059b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13758
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
 2016-02-22 19:32:48 +01:00