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39ff703aa989ebdc056dd27e181fd135a551f522
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10 Commits

Author SHA1 Message Date
Angel Pons
39ff703aa9 nb/intel/pineview: Clean up code and comments 
- Reformat some lines of code
- Put names to all MCHBAR registers in a separate file
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
- Align a bunch of things

Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected.

Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2020-03-15 13:09:19 +00:00
Kyösti Mälkki
df128a55b1 intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL 
This is a PCI standard register, no need to alias its
definitions under different names.

Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-10-01 01:54:08 +00:00
Arthur Heymans
99e578e3c1 nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK 
This adds a file i82801gx/bootblock_gcc.c since other targets that
don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled
bootblock.c.

Tested on Foxconn D41S.

Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-05-25 15:49:27 +00:00
Arthur Heymans
c6ff1ac29e nb/intel/pineview: Move the boilerplate mainboard_romstage_entry 
The mainboard_romstage_entry function is mostly boilerplate, so move
it to a common location and provide mainboard specific callbacks.

Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-01-14 12:02:01 +00:00
Arthur Heymans
b31aee9973 nb/intel/{i945,pineview}: Remove unused function 
Change-Id: I6ca83bde61f231b9f79c90af1d6c1cfa1a027768
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-01-14 12:00:33 +00:00
Arthur Heymans
4bdfebd4d8 nb/intel/pineview: Enable and allocate 8M for TSEG 
TSEG can be used as a stage cache and SMM can be relocated here.

Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25593
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-06-07 06:42:14 +00:00
Martin Roth
128c104c4d nb/intel: Fix some spelling mistakes in comments and strings 
Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17478
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2016-11-21 23:43:54 +01:00
Damien Zammit
51fdb9256a nb/intel/pineview: Native VGA init (CRT) 
VGA grub console works but display wobbles left/right

drm/i915 driver reports one error:
- [drm:i915_irq_handler] *ERROR* pipe A underrun
- Monitor does not display 1920x1080 after modeset
- Other resolutions look out of sync

Cause: suspect single bug in raminit (chipset init)

Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12921
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
 2016-01-28 17:53:47 +01:00
Damien Zammit
f7060f1d0f northbridge/intel/pineview: Add remaining boilerplate code for northbridge 
This patch does *not* include native raminit

Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12430
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
 2015-12-02 00:26:36 +01:00
Damien Zammit
62477931c8 northbridge/intel/pineview: Add minimal Pineview northbridge 
Based on i945.  Tested on Intel D510MO mainboard,
board boots to UART console with this code.

Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10073
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
 2015-11-24 14:40:44 +01:00