Commit Graph

6491 Commits

Author SHA1 Message Date
Sean Rhodes
c436541c3d soc/intel/apollolake: Add UFS Interrupt
According to Intel document number 336561, GLK has UFS (0x1d),
so add the PCI interrupt.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 22:05:11 +00:00
Sean Rhodes
0eb165adf7 soc/intel/apollolake: Remove SD Card interrupt for GLK
According to Intel document number 336561, G, SD Card (0x1b)
does not exist on GLK, so remove it.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 22:04:46 +00:00
Mario Scheithauer
c8c64c12a5 soc/intel/ehl: Set Ethernet controller to D0 power state
To be able to change the MAC addresses, it is necessary that the
controllers are in D0 power state. As of FSP MR3, Intel has set the
controllers to D3 power state at the end of FSP-S TSN GbE
initialization. This patch sets the state back to D0 before the
programming of the MAC addresses.

Test:
- Build coreboot with FSP MR4 for mc_ehl2 mainboard
- Boot into Linux and check MAC addr via 'ip a'

Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07 22:03:45 +00:00
Jeremy Compostella
9159e1c527 soc/intel/alderlake: Support Raptor Lake VR Fast VMODE
RaptorLake introduces the support of the Voltage Regulator Fast Vmode
feature. When enabled, it makes the SoC throttle when the current
exceeds the I_TRIP threshold. This threshold should be between
Iccmax.app and Iccmax and take into account the specification of the
Voltage Regulator of the system.

This change provides a mean to:
1. Enable the feature via the `vr_config->enable_fast_vmode'. If no
   I_TRIP value is supplied FSPs picks an adapted I_TRIP value for
   the current SoC assuming a Voltage Regulator error accuracy of
   6.5%.
2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip'
   field.

These new fields are considered independent from the other `vr_config'
fields so that the board configuration does not have to unnecessarily
supply other VR settings to enable Fast VMode.

Information about the Fast VMode Feature can be found in the following
Intel documents:
- 627270 ADL and RPL Processor Family Core and Uncore BIOS
  Specification
- 724220 RaptorLake Platform Fast V-Mode
- 686872 RaptorLake Lake U P H Platform

BUG=b:243120082
BRANCH=firmware-brya-14505.B
TEST=Read I_TRIP from the Pcode and verify consistency with
     a few `enable_fast_vmode' and `fast_vmode_i_trip' settings.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-07 20:30:16 +00:00
Fabio Aiuto
d835da9155 treewide: use predicates to check for enabled pci devices
use functions to check for pci devices instead of open-coded
solution.

TEST: compiled and qemu run successfully

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06 18:32:21 +00:00
Sean Rhodes
291758ddba soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06 18:20:47 +00:00
Sridhar Siricilla
cb4d464633 soc/intel/meteorlake: Make use of is_devfn_enabled() function
The patch uses is_devfn_enabled() function to enable the TBT PCIe ports
through FSP-M and FSP-S UPDs. Also, removes unused tbt_pcie_port_disable
array member from soc_intel_meteorlake_config struct.

TEST=Build coreboot for Google/Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie55e196bd8f682864b8f74dbe253f345d7184753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-06 18:18:31 +00:00
Michał Żygowski
9baffae485 soc/intel/cmn/gfx: Add missing CML-U IGD device IDs
Intel Core i5-10210U can have the following IGD Device IDs
0x9B21/0x9B41/0x9BAC/0x9BCA/0x9BCC according to Intel ARK. Some of
these IDs were not present in coreboot source nor hooked to the
common graphics driver. Add the missing IDs so that the graphics
driver will probe on the mentioned processor and detect the
framebuffer.

TEST=Boot Protectli VP4650 with i5-10210U and see framebuffer is
detected when using FSP GOP and libgfxinit.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iee720a272367aead31c8c8fa712bade1b6e53948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67975
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06 09:24:54 +00:00
Meera Ravindranath
598c0dda15 soc/intel/alderlake: Fix UFS OCP fabric timeout
The delayed return of certain fetch instruction from memory to
the UFS causes the OCP fabric to timeout on the transaction
and become non-responsive.
As recommended by the SoC and IP teams,program the
OCP fabric register to avoid the timeout in the OCP fabric.

This patch adds the following changes
1. Program the OCP fabric registers in the PS0 routine.
2. Move the ssdt contents of UFS to dsdt asl code to avoid
duplication of UFS device creation

BUG=b:240222922
TEST=Build and boot Nirwen UFS board, observe no system hang
during Chrome PLT test.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-04 18:31:09 +00:00
Lean Sheng Tan
1ec8f97782 soc/intel/adl: Add config option to enable FSP-S SATA test mode
For further info on SATA test mode, please refer to this doc:
https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/sata-mqst-setup-paper.pdf

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I6ef79fc5723348d5fd10b2ac0847191fa4f37f41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 16:50:38 +00:00
Fabio Aiuto
45aae7f10f treewide: use is_enabled_cpu() on cycles over device list
use is_enabled_cpu() on cycles over device list to check
whether the current device is enabled cpu.

TEST: compile test and qemu run successfully with coreinfo
payload

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-29 16:47:04 +00:00
Fabio Aiuto
fdcf698a89 acpi/acpi_pm.c: refactor acpi_pm_state_for_* functions
Use just one function to get the chipset powerstate and add an argument
to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the
failure log accordingly.

TEST: compile tested and qemu emulation successfully run

Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-27 14:19:01 +00:00
Sean Rhodes
9a3e9a495c soc/common/lockdown: Guard sa_lock_pam
Guard sa_lock_pam with PAM0_REGISTER so it doesn't run on platforms
that don't select this.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5055d09c634851e9f869ab0b67a7bcab130f928c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66492
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 18:35:31 +00:00
Sean Rhodes
026f00476e soc/intel/common/pch: Add a block specific to Apollo Lake
Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo
Lake. This is used to select the options that Apollo Lake
requires, without the ones specific to a PCH as Apollo Lake
doesn't have a PCH.

This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for
Apollo Lake.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-22 18:34:33 +00:00
Werner Zeh
826b45b69b common/block/fast_spi: Add extended BIOS window as reserved region
The fast SPI driver reports the BIOS window as reserved so that the OS
is aware of this region. Now that platforms which supports an extended
BIOS window are added to this driver, add the extended range as reserved
as well if it is enabled. And since this is now handled in the SPI
driver itself, remove the extended BIOS region reporting from
common systemagent code.

Change-Id: Ib5c735bffcb389be07c876d7b5b2d88c545a0b03
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-22 15:34:29 +00:00
Werner Zeh
777099046f soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driver
There are two classes of SPI controllers on Intel chipsets:
 * generic usable SPI controllers
 * SPI controller hosting the BIOS flash (fast SPI controller)

While the first class can be used for generic peripheral attachment the
second class mostly controls the BIOS flash and a TPM device (if
enabled). The generic SPI driver is not fully applicable to the fast SPI
controller. In addition, the fast SPI controller reports the reserved
MMIO range used for the BIOS flash mapping so that the OS is aware of
this range.

This patch moves the fast SPI controller of all known SoCs to the
fast SPI driver in common code. In addition, the PCI device for the
fast SPI controller is removed from the function 'spi_soc_devfn_to_bus'
as this is a callback of the generic SPI driver.

Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-22 15:34:24 +00:00
zhaojohn
88a496a9c8 soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence
This patch provides a workaround which skips requesting IOM for D3 cold
entry sequence.

BUG=b:244082753
TEST=Verified MUX configuration after hot plugging Type-C devices on
Rex and MTL RVP boards.

Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-21 15:33:13 +00:00
Tim Wawrzynczak
b525ea726b Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown"
This reverts commit 7ef5376123.

Reason for revert: It was merged before its dependencies so now master is broken.

Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-20 22:00:53 +00:00
Jeremy Compostella
92d3899790 soc/intel/alderlake: Explicitly disable Energy Efficiency Turbo
FSP silicon 3347 changed the default value of the EnergyEfficientTurbo
Updateable Product Data (UPD), enabling the Energy Efficient Turbo
feature by default. This feature prevents the cores from entering
Turbo frequency under heavy load.

As a result of this FSP change, coreboot explicitly disables this
feature to stay consistent with commit `caa5f59279e Revert
"soc/intel/alderlake: Enable energy efficiency turbo mode"'.

BRANCH=firmware-brya-14505.B
BUG=b:246831841
TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc'

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20 08:06:50 +00:00
Gaggery Tsai
517c5a8c54 soc/intel/alderlake: Add power state thresholds
This patch adds power state 1/2/3 threshold setting interfaces
and pass the settings to FSP.

BUG=b:229803757
BRANCH=None
TEST=Add psi1threshold and psi2threshold to overridetree.cb and
     enable FSP log to ensure the settings are incorrect.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-20 08:00:18 +00:00
Arthur Heymans
e247435c6b soc/intel/apollolake: LZ4 Compress FSP-M
FSP-M is not run XIP so it can be compressed. This more than halves
the binary size. 364544 bytes -> 168616 bytes.

On the up/squared this also results in a 83ms speedup.

TESTED: up/squared boots.

Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-09-19 14:57:30 +00:00
Sean Rhodes
9f44a8cc39 soc/intel/apollolake: Add bits of GEN_PMCON2 register
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 14:55:29 +00:00
Sean Rhodes
7ef5376123 soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown
Configure FSP S UPDs to allow coreboot to handle the lockdown.

The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).

The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19 14:55:23 +00:00
Jeremy Soller
c5d0761dea soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID
The Q0 stepping has a different ID than P1.

Reference: CML EDS Volume 1 (Intel doc #606599)
Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-16 16:17:36 +00:00
Jeremy Soller
9601b1e273 soc/intel/alderlake: Set FSP-S GnaEnable based on devicetree
Change-Id: Ifd25416c55c4dba1709f74cdedc0c58e881d6266
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-16 16:17:19 +00:00
Sridhar Siricilla
90a439384b soc/intel/common: Update comment on HFSTS1.spi_protection_mode
The patch updates comment on HFSTS1.spi_protection_mode.
The spi_protection_mode indicates SPI protection status as well as EOM
status (in a single staged EOM flow). Starting from TGL platform, staged
EOM flow is introduced. In this flow, spi_protection_mode alone doesn't
indicate the EOM status.

For information on EOM status, please refer secton# 3.6.1 in doc#
612229.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-16 12:07:06 +00:00
Subrata Banik
a3acac15ee Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"
This reverts commit 510a55d4ee.

Reason for revert: Observed `missing read resource` issue for
cnvi device

BUG=b:244687646
TEST=No error seen in AP log while booting Google/rex

Without this patch:
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0
[ERROR]  GENERIC: 0.0 missing read_resources
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0 done

With this patch:
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0
[SPEW ]  PCI: 00:14.3 read_resources bus 0 link: 0 done

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-16 05:37:05 +00:00
Subrata Banik
00b682e6a4 soc/intel/meteorlake: Enable SOC_INTEL_COMMON_BLOCK_CNVI config
TEST=Able to build and boot Google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I64aab8391f89414754785cea47671f3350324297
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-16 05:36:34 +00:00
Nico Huber
576861994e soc/intel/skylake: Assign device ops in chipset devicetree
Some PCI IDs were missing, and at least one (SPT's fast SPI
device in a generic SPI driver) was wrong. Hence, this patch
actually changes behavior depending on the devices actually
present in a machine.

In this patch the Skylake devicetree is written in a single-line
style. Alternative, the device operations could be put on a separate
line, e.g.
    device pci 00.0 alias system_agent on
            ops systemagent_ops
    end

Tested on Kontron/bSL6. Notable in the log diff is that the
CSE and SATA drivers are hooked up now.

Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-15 13:07:11 +00:00
Elyes Haouas
f1ba7d6c8f soc/intel/xeon_sp: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I664f5b7d354b0d9a7144c25604ae4efbdd9ba9a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-09-15 13:03:28 +00:00
Elyes Haouas
6a8029c2c9 soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia2508abe62a194f2921d5535937ba82a60967ca3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-15 13:02:53 +00:00
Angel Pons
c3aa659286 soc/intel/cannonlake: Read HPR_CAUSE0 register
Log the Host Partition Reset Causes (HPR_CAUSE0) register, as done on
newer platforms.

Change-Id: I35261cefae67649fb7824e5ef3d7eb10add36a53
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-14 14:07:43 +00:00
Rob Barnes
d522f38c7b timer: Change timer util functions to 64-bit
Since mono_time is now 64-bit, the utility functions interfacing with
mono_time should also be 64-bit so precision isn't lost.

Fixed build errors related to printing the now int64_t result of
stopwatch_duration_[m|u]secs in various places.

BUG=b:237082996
BRANCH=All
TEST=Boot dewatt

Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-14 11:55:39 +00:00
Kapil Porwal
715c17a750 soc/intel/mtl: Fix GPIO group pad base for ACPI
This patch fixes MeteorLake GPIO PINCTRL entries as per 5.15
kernel pintrl driver:
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.15/drivers/pinctrl/intel/pinctrl-meteorlake.c

In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation.  The GPIO groups that
are usable by the  OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.

BUG=b:232573696
TEST=Tested on Google Rex board. After this change, driver rt5682s
is able to claim pinctrl IRQ 358 corresponding to GPP_B06.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Icabbe9e125ee9efaf0eef4c4cdc8be9f734aa703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67565
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14 05:29:42 +00:00
Ivy Jian
64c77dc299 soc/intel/meteorlake/retimer: Change loglevel prefix
This message is not really an error message, so BIOS_ERR is 
inappropriate. Since the message is informational, switch to 
BIOS_INFO instead.

BUG=b:244687646
TEST=emerge-rex coreboot
before
[ERROR]  USB Type-C 0 mapped to EC port 0
after
[INFO]  USB Type-C 0 mapped to EC port 0

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ia08fd45dd484c79d81527ea46cfaaa5a01a410c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67536
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-14 05:29:30 +00:00
Ivy Jian
4257e8c132 soc/intel/meteorlake: Enable TcssDma1En
Adding support enables/disables TcssDma1En by usb4_params.

BUG=b:244687646
TEST= TcssDma1En is enabled as expected.
before patch
[SPEW ]  PCI: 00:0d.2 [8086/0000] bus ops
[DEBUG]  PCI: 00:0d.2 [8086/7ec2] enabled
[INFO ]  PCI: Static device PCI: 00:0d.3 not found, disabling it.
after patch
[SPEW ]  PCI: 00:0d.2 [8086/0000] bus ops
[DEBUG]  PCI: 00:0d.2 [8086/7ec2] enabled
[SPEW ]  PCI: 00:0d.3 [8086/0000] bus ops
[DEBUG]  PCI: 00:0d.3 [8086/7ec3] enabled

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I9cd8fc3819f533e9581fea19d4da48283888cc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67534
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14 05:29:23 +00:00
Ivy Jian
78c4d0f6a6 soc/intel/meteorlake: Enable tbtPcie2/3
Adding support enables/disables tbtPcie2/3 by usb4_params.

BUG=b:244687646
TEST= TRP2/3 are enabled as expected.
before patch
[INFO ]  PCI: Static device PCI: 00:07.2 not found, disabling it.
[INFO ]  PCI: Static device PCI: 00:07.3 not found, disabling it.
after patch
[DEBUG]  PCI: 00:07.2 subordinate bus PCI Express
[DEBUG]  PCI: 00:07.2 [8086/7ec6] enabled
[DEBUG]  PCI: 00:07.3 subordinate bus PCI Express
[DEBUG]  PCI: 00:07.3 [8086/7ec7] enabled

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ia1bdc9b5c0533bdddae67b8039103162a57fdc39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67530
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14 05:29:16 +00:00
Srinidhi N Kaushik
f4a8a92cc2 src/soc/intel/mtl: Remove Storage UPD
This change removes all references to HybridStorageMode
UPD since it has been deprecated starting from FSP v2344_00

BUG=b:245167089
TEST=build coreboot mtlrvp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I16eb33cb1260484b0651d40211323c6ae986a546
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12 12:32:12 +00:00
Lean Sheng Tan
cf46099979 soc/intel/adl: Disable D3cold when legacy S3 is enabled
D3Cold isn't supported in S3.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I072f47737ef38c44b6a676019e9a73868ff17e5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67413
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12 12:24:09 +00:00
Subrata Banik
2bce51ea2a soc/intel/meteorlake: Hook up common code for thermal configuration
Thermal configuration registers are now located behind PMC PWRMBASE
for MeteorLake as well (same as ADL). Hence, using thermal common code
to sets the thermal low threshold as per mainboard provided
`pch_thermal_trip`.

Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.

TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on
Google/rex prior to FSP-S shows that registers are now programmed
based on 'pch_thermal_trip' and lock register BIT31 is set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10 19:00:56 +00:00
Subrata Banik
8b518776da soc/intel/meteorlake: Update pch_thermal_trip for MTL
This patch updates `pch_thermal_trip` as per Intel MTL vol1
chapter 14.

Additionally, dropped the `FIXME` tag for `pch_thermal_trip`.

TEST=Able to boot the Google/rex to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10 19:00:49 +00:00
Subrata Banik
f5afc1a5a2 soc/intel/meteorlake: Drop redundant MCHBAR programming in romstage
This patch drops redundant MCHBAR programming in romstage as bootblock
already done with MCHBAR setting up.

TEST=Able to boot Google/Rex to ChromeOS and MCHBAR is set to correct
value as per iomap.h

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic2c05f47ab22dc7fe087782a1ce9b7b692ea157e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-10 19:00:39 +00:00
Subrata Banik
a3ad319fbf soc/intel/meteorlake: Disable FSP UPDs related to virtualization
This patch disables FSP UPDs (`VtdDisable` and `VmxEnable`) as kernel
cmdline still passes `intel_iommu=off` to turn off virtualization.

BUG=b:241746156
TEST=Able to boot Google/rex to ChromeOS UI.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I21e178a93e311889f2ab7d1a08230d21b051f45e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67452
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-10 18:59:37 +00:00
Subrata Banik
4cc8a6ccce soc/intel/meteorlake: Hook up PAVP to Kconfig
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for multimedia
content) to Kconfig.

TEST=Able to boot Google/rex to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I416346995d744990054c8e0c839ada82c84b7550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67423
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08 16:42:05 +00:00
Sean Rhodes
f251660a0e soc/intel/common/smbus: Add missing ID for GLK
PCI ID taken from Intel doc #569262.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I31d4b7edf3288794c86a6d2b78acdc4cf0ac611f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08 15:33:35 +00:00
Sean Rhodes
e7bdc1b9e0 soc/intel/commmon/fast_spi: Add missing ID for GLK
PCI ID taken from Intel doc #569262.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5812e536f3e1c49a272a0b337cc69f3d8f30677f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08 15:33:20 +00:00
Simon Yang
a16ed34638 soc/intel/alderlake: add power limits for Alder Lake-N 7W soc
Missing power limit setting for Alder-Lake-N 7W soc.
Document reference: 645548 and 646929

BUG=b:245440443
BRANCH=None
TEST=Build FW and test on nivviks board and there is no error
message "unknown SA ID: 0x4617, skipped power limits configuration."

Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-08 14:19:57 +00:00
Martin Roth
9228f9e49a src/soc/intel: remove force-included header compiler.h from file
The header file `compiler.h` is automatically included in the build by
the top level makefile using the command:
`-include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h`.

Similar to `config.h`, 'kconfig.h`, and 'rules.h`, this file does not
need to be included manually, so remove it.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06 17:57:51 +00:00
Martin Roth
7a9716bb45 src: remove force-included header rules.h from individual files
The header file `rules.h` is automatically included in the build by the
top level makefile using the command:
`-include src/soc/intel/common/block/scs/early_mmc.c`.

Similar to `config.h` and 'kconfig.h`, this file does not need to be
included manually, so remove it.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67348
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-06 17:57:31 +00:00
Subrata Banik
8409f156d5 soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei Module
This patch fixes a hidden issue present inside FSP-S while coreboot
decides to skip performing MP initialization by overriding FSP-S UPDs
as below:
 1. CpuMpPpi  ------> Passing `NULL` as coreboot assume FSP don't need
                      to use coreboot wrapper for performing any
                      operation over APs.

 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided
                      to skip FSP running CPU feature programming.

Unfortunately, the assumption of coreboot is not aligned with FSP when
it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of
the APs (Application Processors) upon passing `NULL` pointer to the
`CpuMpPpi` FSP-S UPD.

FSP-S creates its own infrastructure code after seeing the CpuMpPpi
UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker`
to perform those additional initialization which is not relevant for
the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid
running CPU feature programming on APs).

Additionally, FSP-S binary size has increased by ~30KB (irrespective of
being compressed) with the inclusion of the CpuMpPei module, which is
eventually not meaningful for coreboot.

Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config
unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD
and avoid APs getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.

Ideally, FSP should have avoided all AP related operations when
coreboot requested FSP to skip MP init by overriding required UPDs.

TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on
Google/Redrix, Kano, Taeko devices with SkipMpInit=1.

Without this patch:

Here is the CPU AP logs coming from the EDK2 (open-source)
[UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the
CpuMpPpi UPD.

[SPEW ]  Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6
[SPEW ]  Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2
         CpuMpPei.efi PROGRESS CODE: V03020002 I0
[SPEW ]  Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
[SPEW ]  Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE,
         Peim notify entry point: 76FA0239
AP Loop Mode is 2
GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found.
CPU[0000]: Microcode revision = 00000000, expected = 00000000
[SPEW ]  Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6
Does not find any stored CPU BIST information from PPI!
  APICID - 0x00000000, BIST - 0x00000000
[SPEW ]  Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97
[SPEW ]  Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA
[SPEW ]  Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A
PROGRESS CODE: V03020003 I0

With this patch:

No instance of `CpuMpPei` has been found in the AP UART log with FSP
debug enabled.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8ebe0bcfda513e79e791df7ab54b357aa23d295c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66706
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-05 14:08:02 +00:00