3e3d969e6f
src/: Chmod 644 all .c, .h, .asl, .inc, .cb, .hex, & Kconfig files
...
Some trivial cleanup.
Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914
Signed-off-by: Martin Roth <martinroth@google.com >
Reviewed-on: https://review.coreboot.org/13427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2016-01-29 16:57:11 +01:00
103f00daab
intel/strago: Remove support for older rev boards
...
Cleaning up code to remove support for early revs of Strago board
Change-Id: Ic0647a17d78164fd7dfadc731c9395a8ba08c235
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Reviewed-on: https://review.coreboot.org/13434
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com >
2016-01-28 20:36:35 +01:00
26f64069d2
soc/braswell: Configure Boot Flash Write Protect status GPIO
...
Set up the GPIO(MF_ISH_GPIO_4) to read WP status.
TEST=Use crossystem to read the WP status
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff
Original-Reviewed-on: https://chromium-review.googlesource.com/302424
Original-Tested-by: John Zhao <john.zhao@intel.com >
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com >
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Reviewed-on: https://review.coreboot.org/13185
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com >
2016-01-28 20:35:59 +01:00
c681638116
intel/strago: Enable native mode on sd card cd line
...
Configuring Native Mode enables the card present bit in
sd card controller register.
TEST=Sd Card Plug/Unplug should work in OS and DepthCharge.
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org >
Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com >
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Reviewed-on: https://review.coreboot.org/12741
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com >
2016-01-28 20:35:35 +01:00
1d03f36887
intel/strago: Disable unused lines on Gpio North Bank
...
The unused lines leads to spurious interrupts
on few of the systems.
TEST=run suspend_stress test and make
sure that kbd is working.
Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com >
Original-Reviewed-on: https://chromium-review.googlesource.com/313417
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Reviewed-on: https://review.coreboot.org/13176
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com >
2016-01-28 20:35:13 +01:00
116d67323b
intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue.
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LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage
TEST=Test on Strago and make sure the leakage is gone
Signed-off-by: Kane Chen <kane.chen@intel.com >
Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352
Original-Reviewed-on: https://chromium-review.googlesource.com/317020
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org >
Original-Tested-by: Kane Chen <kane.chen@intel.com >
Original-Commit-Queue: Kane Chen <kane.chen@intel.com >
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Reviewed-on: https://review.coreboot.org/13175
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com >
2016-01-28 00:04:19 +01:00
2abcffcc40
intel/strago: EC_IN_RW gpio input configuration.
...
Configure EC_IN_RW signal as gpio input.
TEST=Boot to Chrome OS in normal mode and enter recovery mode
use ctrl-d to switch to Dev mode.
Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Original-Reviewed-on: https://chromium-review.googlesource.com/304040
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com >
Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com >
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com >
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com >
Reviewed-on: https://review.coreboot.org/13124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com >
2016-01-28 00:03:12 +01:00
d4b26b2923
intel/strago: Fix GPIO config
...
Fix GPIO config for this board:
- SD card detect to GPI
- SATA GPI to not used
- GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination
- I2C4 SDA and SCL from not used to Native
Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2
Signed-off-by: Hannah Williams <hannah.williams@intel.com >
Reviewed-on: https://review.coreboot.org/13431
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com >
2016-01-27 23:58:11 +01:00
a73b93157f
tree: drop last paragraph of GPL copyright header
...
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org >
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com >
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com >
2015-10-31 21:37:39 +01:00
367ddc91ff
cyan/strago: Disable wwan
...
Disabling the wwan gpio line
since wwan is not used.
BRANCH=none
BUG=none
TEST=wwan should not connect to network on cyan/strago.
Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org >
Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef
Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com >
Original-Reviewed-on: https://chromium-review.googlesource.com/285304
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-on: http://review.coreboot.org/10992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2015-07-21 20:08:41 +02:00
5cb9ddad3e
mainboard/intel: Add Braswell based Strago board
...
Add the initial files to support the Intel RVP for Braswell.
Matches chromium tree at 927026db
This board uses the Braswell FSP 1.1 image and does not build without
the FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run ChromeOS on strago
Change-Id: I5cb2efe3d8adf919165c62b25e08c544b316a05a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com >
Reviewed-on: http://review.coreboot.org/10052
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2015-07-17 20:18:34 +02:00
