Create the bugzzy variant of the waddledoo reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192521391
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BUGZZY
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I851b9a75c387586d2fb84b762788e962f33472b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56762
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add current maintainers for vboot-related code, and combine the vboot
and vboot2 sections which are not really separate anymore. What's left
in vendorcode/google/chromeos isn't really related to vboot anymore
since the vboot code was moved under src/security, so take it out of
there.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I59a2df9c1580291a6d29537868aab0e1b339a2ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The all shipped magolor and maglia has SSFC= 0x840.
The value is defined as 5M MIPI camera.But the value:0x840 will
conflict with the updated touchscreen field.
It will cause some touchscreen no function if make auto-update new
firmware.The CL would correct the field error.
The original fields:
CAMERA_WFC 38 40
TS_SOURCE 41 44
Correct fields:
MIPI Cam
CAMERA_WFC 38 40
CAMERA_UFC 41 42
CAMERA_VCM 43 44
Touch-screen
TS_SOURCE 45 48
The SSFC value of Magolor:
CAMERA_OVTI5675 5M AF (SSFC = 0x840)
CAMERA_OVTI8856 8M AF (SSFC = 0x880)
BUG=b:194639170
TEST=Build firmware and verify on camera and touch-screen devices
Change-Id: I13d76ce8b932f483e20ca5388f1c67eb39ba12a1
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56685
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DDI 0/1 ports are shared for DP and HDMI. This implementation
adds support for HDMI display when HDMI is set as connector type
in ddi descriptors.
TEST=verify display over HDMI(0 and 1) in OS.
Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: I9697211c556f12d1fc0d49418b227fbe6b342673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move elog_internal.h to commonlib/bsd/include/bsd/.
And rename it from elog_internal.h to elog.h.
Since this file will be included from util/ it also converts the "uNN"
types into "uintNN_t" types.
The two defines that are not used by util/ are moved to
drivers/elog/elog.c, the only file that includes them.
Move also the function elog_verify_header() from drivers/elog/, to
commonlib/bsd/elog.c since this function will be called from util/
as well.
The rationale behind moving elog's defines & structs to
commonlib/bsd/include is to make them available to util/ tools and/or
payloads (should it be needed in the future).
The files that are being relicensed to BSD were coded by Duncan Laurie,
and he is Ok with the relicense.
BUG=b:172210863
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ia1aefea705ddd417a1d9e978bb18ab6d9a60cad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move post_codes.h from include/console to
commonlib/include/commonlib/console.
This is because post_codes.h is needed by code from util/
(util/ code in different commit).
Also, it sorts the #include statements in the files that were
modified.
BUG=b:172210863
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sometimes it's preferable or even necessary (e.g. stability issues) to
limit the maximum package C state. Let's add a devicetree option that
keeps the current behavior if it is left unset.
Change-Id: I0dc254d34f46de4c65cb85cc92e4b7f26618888d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add basic devapc (device access permission control) drivers.
DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.
1. Initialize devapc.
2. Set master domain and secure side band.
3. Set domain remap.
4. Set default permission.
Change-Id: I3677657a117caed0d73526f78b0ebe8180148335
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 6 and provide the reset GPIO / src clk pins.
BUG=None
BRANCH=None
TEST=Build and boot the coreboot image, check if device is enumerated
in the lspci list after warm/cold reboot cycles, run suspend cycles and
check if WWAN is entering L2 LPM.
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
- configure TROGDOR_HAS_MIPI_PANEL to "n" by default, it can be updated for mipi panels.
- add simple rm69299 panel as an example to append new mipi panels.
- use existing edid struct to update mipi panel parameters.
- add dsi command tx interface for mipi panel on commands.
Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52662
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Crashlog is a debug feature and not used in normal mode of operation.
Disabling this feature will allow us to disable unused IPs and also
provide boot time savings of ~5-7 ms.
BUG=b:195327879
BRANCH=None
TEST=Platform boots and no function impact
Change-Id: I1f7def4ea41ff7a566aada080be1e791c11766e6
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56654
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file only contains the `broadwell_run_reference_code()` function
prototype (either a declaration or an inline stub definition). Rename
this file to refcode.h and only include it where necessary.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I6513f45b8914a84312b27ef4860870a89fd0aab3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55582
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update tianocore branch used with default UEFIPAYLOAD option to
mrchromebox/uefipayload_202107 (July 2021) branch. This branch is
rebased on edk2 upstream commit 12e34cd2f7900578ee83cb01b8f1696a7bb7511b
[OvmfPkg/Bhyve: clean up TPM_ENABLE remnants] vs tag edk2-stable202105.
The main changes are fixes for e820 table parsing and support to disable
"Above 4G decode", which is required to boot distros with bootloaders
that expect to be loaded into RAM below 4G. This fixes booting with
Qubes, ZorinOS, Proxmox, among others.
Additionally, several commits on top of upstream have been consolidated,
reworked, and/or reordered for readability and maintainability.
Change-Id: I6f04fd027a0599ca6892a1376938108a2e402ac2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some legacy devices need to have the master bit set in the PCI config
due to old drivers not setting it correctly. Set the master bit if the
feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE.
For now, the PCI devices with the ID 110a:403e and 110a:403f needs this
master bit to be set.
Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56632
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boards based on mc_ehl have, just like some mc_apl variants, legacy
devices on the PCI bus which take longer to boot. In order to ensure
that they will be enumerated correctly wait for them to come up before
PCI scan starts.
TEST=Checked that the new message is visible in the log.
Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56631
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GENMASK is defined in multiple files (with various names such as
MASKBIT), which sets certain consecutive bits to 1 and leaves the others
to 0. To avoid duplicate macros, add GENMASK macro to helpers.h.
GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For
example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000.
Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in
mmio.h.
BUG=none
TEST=make tests/commonlib/bsd/helpers-test
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As per the schematics, UFC has on card oscillator so we donot need
H21 in NF1 that is IMGCLKOUT
H21 is used to enable this oscialltor so configuring it as 1
A17 is configured as high while _ON method is called by driver and
it is configured as low when _OFF method is called by driver.
Hence coreboot should configure it as low on boot.
BUG=b:190674542
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56655
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
