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Author SHA1 Message Date
Kane Chen
c023839a84 mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz 
Since Jelboz support number pad,
due to one single coreboot for both Jelboz and Shuboz,
modify "overridetree.cb" setting to number pad support for Jelboz.

BUG=b:174964012
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
 2021-02-10 16:03:08 +00:00
Felix Held
35b3cc9b6d soc/amd/block/psp/psp: raise log level of PSP failure messages 
If the PSP didn't like a command this should be at least a warning on
the console and not just a debug message.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 14:45:21 +00:00
Elyes HAOUAS
6564842857 sb/amd/cimx/sb800/acpi: Convert to ASL 2.0 syntax 
Also, fix typo on "success".
Built gizmosphere/gizmo generate identical 'build/dsdt.dsl'.

Change-Id: I6fd7056d8053f0097b5c9de6b4e2e6db38910a2e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 09:25:49 +00:00
Elyes HAOUAS
b5a237d911 sb/amd/pi/hudson/acpi/fch.asl: Convert to ASL 2.0 syntax 
Change-Id: Ie413f36ef11a42a23d7d265d7a66f5e0d088892e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 09:25:35 +00:00
Angel Pons
6b486e1588 soc/intel/broadwell/pch: Simplify PCI RMW operations 
This reduces the differences between Lynx Point and Broadwell.

Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 07:33:35 +00:00
Angel Pons
4299cb4829 nb/intel/i945: Use common {DMI,EP,MCH}BAR accessors 
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: If6d6cba76bdd1134372ab2faa475e574fdc5fddf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:30:05 +00:00
Angel Pons
e88f705946 nb/intel/x4x: Use common {DMI,EP,MCH}BAR accessors 
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I33c17f56eac0277a12b32af777e2e1ceb086685f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:29:54 +00:00
Angel Pons
24b1d8af06 nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors 
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: Ic390d3431e2aa9f5f59cb266d4c358d0eb48576c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:29:46 +00:00
Angel Pons
a8df6cff16 nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessors 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:29:29 +00:00
Angel Pons
d9e58dca9e nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors 
Drop unused sandybridge.h includes to avoid build failures on Ironlake.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:29:14 +00:00
Angel Pons
a2a9e607b1 soc/intel/broadwell: Use common MADT code 
Save for some cosmetic differences, the code is equivalent.

Change-Id: I48d4b522009eee9053d247217ca03d8bfea80cdf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:28:12 +00:00
Angel Pons
f21e5c06cd soc/intel/broadwell/pch: Drop acpi_sci_irq function 
The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using
common MADT code on Broadwell, hardcode it as 9 everywhere.

Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-10 07:27:57 +00:00
Julius Werner
e0f058ffa8 coreboot_table: Use precision when printing lb_gpio name 
The lb_gpio coreboot table entries use name fields fixed to 16 bytes.
GCC will not allow creating a static initializer for such a field with a
string of more than 16 characters... but exactly 16 characters is fine,
meaning there's no room for the terminating NUL byte. The payloads (at
least depthcharge) can deal with this as well because they're checking
the size when looking at that table entry, but our printk("%16s") does
not and will happily walk over the end until somewhere else in memory we
finally find the next NUL byte.

We should probably try to avoid strings of exactly 16 characters in this
field anyway, just in case -- but since GCC doesn't warn about them they
can easily slip back in. So solve this bug by also adding a precision
field to the printk, which will make it stop overrunning the string.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd7beef00d828f9dc2faa4747eace6ac4ca41899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-02-10 07:27:38 +00:00
Elyes HAOUAS
caef68968c mb/intel/adlrvp/bootblock.c: Remove unused includes 
Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-02-10 07:26:46 +00:00
Elyes HAOUAS
9bbb108f24 mb/emulation/qemu-q35/bootblock.c: Remove unused includes 
Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-02-10 07:26:22 +00:00
Elyes HAOUAS
19b66235aa mb/gizmosphere/gizmo2/bootblock.c: Remove unused includes 
Change-Id: Ibdc94e59ffa345670bbed246e94b02a7148a1971
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-10 07:25:47 +00:00
Sheng-Liang Pan
076d9b9778 mb/google/volteer/var/voxel: Add settings for noise mitgation 
Enable acoustic noise mitgation for volteer platforms.

BUG=b:179328166
BRANCH=none
TEST= Measure the change in noise level by changing the values
in devicetree.

Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2021-02-10 07:25:33 +00:00
Benjamin Doron
448ecc0e06 soc/intel/{cnl,skl}: Add alignment check for TSEG base and size 
Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG
base and size) to remaining SoCs.

Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 07:24:32 +00:00
Shreesh Chhabbi
3c6ad8d184 mb/google/volteer: Enable external bypass, clkgate & phygate 
This change sets the soc config options for external_bypass,
external_clk_gate and external_phy_gate.

BUG=b:177821896
TEST=Build coreboot for volteer

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 07:23:22 +00:00
Shreesh Chhabbi
fbad99f347 soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design 
This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):

1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH

In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. Deepest state expected on tigerlake up3 based
platforms is S0i3.2.

BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest
S0ix substate that is enabled is S0i3.1

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 07:23:09 +00:00
Paul Menzel
79cc5e01b8 mb/google/zork: devicetree: Fix typo in *Coprocessor* in comment 
Fixes: b3c41329fd (mb/google/zork: Add Picasso based Zork mainboard and variants)
Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-10 07:22:51 +00:00
Lijian Zhao
94e4961a01 acpi: Fix Coverity Scan report 
Fix the issue that return value "r" in line 534 will get overwritten
problem.

BUG=CID 1445995
TEST=Build sucessful and boot up in QEMU

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Icf760b142cfecfed7c929c15ad190ac74df027b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-10 07:22:35 +00:00
Elyes HAOUAS
f7a7e65aa4 src: Remove unused <boot_device.h> 
Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50201
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 07:22:08 +00:00
Angel Pons
80594b79f9 mb/prodrive/hermes: Set Port C VREF as per EEPROM config 
Configure Port C VREF according to the settings in the EEPROM.

Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50396
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 07:21:32 +00:00
Angel Pons
082b36009c mb/prodrive/hermes: Configure 'internal audio' 
Implement `mainboard_azalia_program_runtime_verbs` to configure the
Realtek ALC888 codec according to the settings in the EEPROM. The
encoding of the `internal_audio_connection` field is:

0: Disabled
1: Front HP out
2: Internal speaker

Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-02-10 07:21:22 +00:00
Angel Pons
d6d71ce442 device/azalia_device: Add mainboard hook to program codecs 
On some mainboards, codec configuration depends on settings that are
only known at runtime, which is impossible to specify using one verb
table. Add an optional `mainboard_azalia_program_runtime_verbs` hook
where mainboards can program runtime-dependent codec verbs.

Change-Id: I7efeba5c26051aeb5061cce191ace08c304a6c70
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-02-10 07:21:11 +00:00
Angel Pons
44c431e161 device/azalia_device: Add function to program a verb table 
On some boards, Azalia configuration depends on config settings that are
not known at compile-time. Expose a function to program a verb table, to
be used in subsequent commits.

Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-02-10 07:21:00 +00:00
Angel Pons
2e77443e47 device/azalia_device.c: Correct print format 
The type of `verb_size` is unsigned, thus use `%u` to print its value.

Change-Id: I2b353b940e881dc8b5f0b902509d97d89c997a70
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-02-10 07:20:50 +00:00
Angel Pons
06d224f65e nb/intel/x4x: Correct DDR3 turnaround table 
Comparing against MRC, looks like the values for TA3 and TA4 are
backwards. All of them. Thus, correct the tables accordingly.

Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works.

Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4
Tested-by: Michael Büchler <michael.buechler@posteo.net>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49388
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Büchler <michael.buechler@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 07:20:38 +00:00
Patrick Rudolph
082f0b94ee mb/prodrive/hermes: Set mb_hda_amp_enable based on cfg 
Change-Id: I13c2ece729128fe245de88c0d36ce7b4bcaf6b6d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 07:20:14 +00:00
Patrick Rudolph
6c2f34ab32 mb/prodrive/hermes: Drop reset functions 
The reset GPIOs are already configured in bootblock.
Drop the unused ramstage code.

Change-Id: Ic99fcae2a3f00be7eebd7be618df838522dac69f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 07:19:48 +00:00
Mario Scheithauer
1cd95b0acf mb/siemens/mc_apl2: Switch I2C bus for RX6110SA 
With a new HW revision of this board, the connection of the external RTC
RX6110SA was changed from I2C bus 0 to I2C bus 3.

Change-Id: I10dd44949973ea490b3c7e4ad83d56ce2e566adf
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-10 06:22:09 +00:00
Felix Held
a3544e47fb soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_util 
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50415
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 01:32:03 +00:00
Felix Held
063fc1747a soc/amd: Move global_smi_enable to common/blocks/smi/smi_util 
Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42989
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 01:31:39 +00:00
Felix Held
1a973434c5 soc/amd: Move soc_route_sci to common/blocks/smi/smi_util 
Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42988
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 01:31:28 +00:00
Kyösti Mälkki
2fec394913 soc/amd/picasso: Move APM_CNT_SMMINFO callsite 
Triggering SMI is not part of the semantics of global_smi_enable(), so
move it to the post_mp_init handler. Even without the !acpi_is_wakeup_s3
check we don't get PSP warnings/errors during resume, so we can drop the
workaround introduced in commit 5dbe45e0f5
in this patch.

Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42987
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 01:31:09 +00:00
Elyes HAOUAS
708e4cb596 mb/amd/gardenia: Convert to ASL 2.0 syntax 
Change-Id: I8c8845ed6eb466acff568247184c6ad6b186e9ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46145
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 00:30:57 +00:00
Elyes HAOUAS
db53013b18 mb/amd/olivehill: Convert to ASL 2.0 syntax 
Change-Id: Icacd8c8a7b5604354a7fd04ed73ecb3bbc86e669
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46147
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 00:30:35 +00:00
Elyes HAOUAS
67444fb952 mb/jetway/nf81-t56n-lf: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' are same.

Change-Id: I16eceec980c10e77f2a0aec9a420437d03fc2352
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46187
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 00:30:13 +00:00
Elyes HAOUAS
f232d30f38 mb/amd/persimmon: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I492118c9287b5853e8784a6de6bc514e97c93e96
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46150
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 00:29:56 +00:00
Elyes HAOUAS
5e03bd4f6d mb/amd/south_station: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I52c33679fbb7e9807423fc0fcc470e54105013db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46151
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 00:29:41 +00:00
Elyes HAOUAS
94bcbca32f mb/amd/union_station: Convert to ASL 2.0 syntax 
Generated build/dsdt.dsl are identical.

Change-Id: I8127b5b22e2822f4ace07c28409e501c3fcb309b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46153
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 00:29:14 +00:00
Elyes HAOUAS
e963532a96 mb/amd/inagua: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I0ee0d2b83cbfd81fab43eec255bcc214b9543f82
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46146
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 00:27:43 +00:00
Elyes HAOUAS
b9c5445638 sb/amd/common/acpi: Convert 'sleepstates.asl' to ASL 2.0 syntax 
Change-Id: I16919a0fd5a78d666dc7003d4e495fd41c24613d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2021-02-10 00:21:59 +00:00
Elyes HAOUAS
0a76e7a493 sb/amd/{agesa,pi}hudson/acpi: Convert 'pci_int.asl' to ASL 2.0 syntax 
Change-Id: I1a382eaf122e40aeaefedf88425749616a2090d9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2021-02-10 00:19:41 +00:00
Elyes HAOUAS
668cad1c9d mb/gizmosphere/gizmo: Convert to ASL 2.0 syntax 
Built for gizmosphere/gizmo (Gizmo), it provides identical dsdt.dsl file.

Change-Id: I8647080cda7715d323d38f93c33176dfe9608652
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2021-02-10 00:10:00 +00:00
Elyes HAOUAS
a81c46180c sb/amd/{agesa,pi}hudson/acpi: Convert 'AmdImc.asl' to ASL 2.0 syntax 
Change-Id: Ica6998026031e1b3d7286ce74a2334237d29ac74
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2021-02-10 00:09:43 +00:00
Elyes HAOUAS
0f21996c1d mb/lippert/frontrunner-af/acpi/sata.asl: Convert to ASL 2.0 
Change-Id: Ife718dcec765d3b2861bce16f9ca2b6355166800
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2021-02-10 00:09:16 +00:00
Elyes HAOUAS
3759e26c87 sb/amd/agesa/hudson/acpi/fch.asl: Convert to ASL 2.0 
Change-Id: I8903450b505701e1fd62c1a70b896a4dfb37d5a1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2021-02-10 00:08:20 +00:00
Elyes HAOUAS
01ae7e7de6 sb/amd/{agesa,pi}/hudson/acpi: Convert 'audio.asl' to ASL 2.0 syntax 
Change-Id: I976b4c2e2aa878d8b591c3e416ffb76d7a699b39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-10 00:07:55 +00:00