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Author SHA1 Message Date
Kyösti Mälkki
864be5bae5 mainboards: Remove default CHROMEOS=y 
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested
with CHROMEOS=n.

Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-02-04 07:03:44 +00:00
Kyösti Mälkki
dc15505795 vc/google/chromeos: Drop <acpi/vpd.asl> 
This was used as a means to read the MAC address and dynamically
return it to the ethernet driver via ACPI. The kernel team ended
up going another direction so this became obsolete.

Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 07:02:03 +00:00
Kyösti Mälkki
07bce4ba36 coreboot_table: Convert some CONFIG(CHROMEOS) preprocessor 
Change-Id: I0c42720fdcc3b05337af692ed93a424575defd36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48786
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 07:00:32 +00:00
Kyösti Mälkki
563c860c0f coreboot_table: Drop <vboot/misc.h> include 
Could have been removed with commit 63b9700b2c already.

Change-Id: Ie1083bce1794613c7dc683ae533e42fb5af39adf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50249
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 06:59:54 +00:00
Kyösti Mälkki
368c9a1847 vc/../chromeos.asl: Drop CHROMEOS guard 
coreboot proper now has a single include for this file
with the guard around it already.

Change-Id: Ice48a6af391170232a0319cc894bdb6c465c5143
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-02-04 06:58:51 +00:00
Felix Held
65fd33f95f vendorcode/amd/fsp/cezanne: add UPD structs from FSP build 
There will be incompatible changes during the further development of the
coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct
size to match the one in the FSP header. See CB:50241 for details.

Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 01:36:04 +00:00
Felix Held
c0dbd4cb56 soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers 
Picasso has 32 configurable GPEs, not only 28.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-04 00:10:20 +00:00
Felix Held
404aea866c amd/common/block/acpi/pm_state: fix comparison in get_index_bit 
In the case of passing 32 as limit the code returned -1, but should have
continued, since 32 is a valid value here.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-04 00:10:02 +00:00
Wayne3_Wang
585f4d46cc mb/google/volteer/variants/drobit: Configure USB2 port for Type-C 
USB2 ports assigned to type-C connector need to be configured properly
by the USB2_PORT_TYPE_C. and also modify the description of USB port.

BUG=b:177480902
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the typeC port function is normal by manual.

Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 20:11:40 +00:00
Derek Huang
ed6bda2818 soc/intel/tgl: Add configurable value for ConfigTdpLevel 
According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level

Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2021-02-03 20:11:06 +00:00
David Wu
e65e9dd6b1 mb/google/volteer/var/voema: Enable EEPROM for OV2740 
Add ACPI entries for AT24 NVM device.

BUG=b:169551066
TEST=Build and run for basic camera functions.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-03 20:04:59 +00:00
Felix Held
ee1fb0aa1a soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports 
There's no dedicated south bridge any more and now we have integrated
FCHs in the SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 20:00:48 +00:00
Felix Held
70f1af8934 soc/amd/cezanne: remove UART2/3 AOAC device offsets 
UART2 and UART3 don't exist on Cezanne which now has been verified, so
remove the corresponding AOAC offsets.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-03 19:59:54 +00:00
Chris Wang
4c4a360018 soc/amd/picasso: clean up and re-sort UPD table 
Clean up the unused UPD and re-sort the table, and also update
the new phy parameter in the soc code and overridetree.

remove:
	EDpPhySel
	EDpVersion
rename:
	DpPhyOverride -> edp_phy_override
	EDpPhySel -> edp_physel
	DpVsPemphLevel -> edp_dp_vs_pemph_level
	MarginDeemPh -> edp_margin_deemph
	Deemph6db4 -> edp_deemph_6db_4
	BoostAdj -> edp_boost_adj

eDP phy setting:
    DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0)
    COMMON_MAR_DEEMPH_NOM = 0x004b
    COMMON_SELDEEMPH60 = 0x0
    CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80

BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2021-02-03 17:27:30 +00:00
Zhuohao Lee
275440edf1 mb/google/volteer/variant/copano: support regular/numpad touchpad 
Define the 25th bit of the fw_config for the regular touchpad
and numpad touchpad selection.

BUG=b:174027837
BRANCH=firmware-volteer-13672.B
TEST=build pass

Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-03 17:23:05 +00:00
Subrata Banik
c5cc741fe9 vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037 
List of changes:
1. FSP-M Header:
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx

Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-03 15:50:10 +00:00
Zheng Bao
b993cb2d6c amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) 
Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-03 13:48:51 +00:00
Pablo Stebler
a5ce4d3e68 ec/hp/kbc1126: Wait a longer time after sending 
This fixes the fan always running at full speed on ProBook 6360b,
EliteBook 8470p and ProBook 640 G1 (because the fan control command was
not sent).

On the ProBook 6360b, the EC needs about 30 ms to process the first
command on a cold boot, but other models such as the ProBook 640 G1 need
more time.

Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb
Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-03 11:52:44 +00:00
Nico Huber
19dd694401 pci_ids/intel: Add missing CFL-S GT1 IGD IDs 
Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
 2021-02-03 08:58:39 +00:00
Nico Huber
1b5e855347 pci_ids/intel: Correct 0x3e96, it's a CFL-S part 
Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-02-03 08:58:33 +00:00
Elyes HAOUAS
39df11f104 src: Remove unused <boardid.h> 
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
 2021-02-03 08:56:39 +00:00
Elyes HAOUAS
0322bc5ed8 src: Remove unused <cbmem.h> 
Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-02-03 08:56:35 +00:00
Elyes HAOUAS
a684d677fb soc/ti/am335x/header.c: Add missing include 
Use of 'offsetof' needs <commonlib/bsd/helpers.h>.

Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:55:15 +00:00
Wayne3_Wang
49e1140879 mb/google/volteer/variants/drobit: Modify touchpad I2C sequence 
Modify touchpad I2C sequence to meet requirement.

BUG=b:178512111
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the touchpad I2C5 sequence by EE.

Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Iebbeeec51b802c318ac014dcdd2603b600d931a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49958
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:54:54 +00:00
Wayne3_Wang
df7d4fc297 mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit 
Add the TBT PCIE rp setting to on and also fixes system hang
in recovery screen after selected "Power off" item problem.

BUG=b:177963941
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the system can power off normally in recovery page

Cq-Depend: chrome-internal:3581043
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:54:41 +00:00
Johnny Lin
a70ebdf289 intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selected 
Because ACM already does TPM initialization.

Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-02-03 08:54:02 +00:00
Neill Corlett
ed7ebc26fa hatch: Update fan and thermal settings for ambassador 
Update fan and thermal settings for ambassador, per recommendations from
Quanta.

BUG=b:177765580
TEST=Built AP firmware

Change-Id: I080859f872caf696f0c085defb8372de658da58a
Signed-off-by: Neill Corlett <corlett@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50100
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Joe Tessler <jrt@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:53:41 +00:00
Elyes HAOUAS
3cf3635d23 mb/biostar/th61-itx/early_init.c: Clean includes 
Change-Id: I0619e567527812bd0e7088d23d91f114c8fec9ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-02-03 08:53:27 +00:00
Patrick Rudolph
dec2c78403 drivers/aspeed: Fix some issues 
* Use probe_resource instead of find_resource. This prevents
  a call to die and instead returns NULL.
* Handle the case where BAR2 isn't present
* Don't hardcode legacy VGA when BAR2 is present. This fixes
  graphic initialisation when the Aspeed isn't the primary GPU
  and thus doesn't decode VGA cycles.

This makes the coreboot code more similar to the Linux kernel code.

Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:53:10 +00:00
Angel Pons
6d7a6d291d mb/google/sarien: Turn hda_verb.h into hda_verb.c 
Change-Id: I40c8145fdddf9605bc3cc66ae8075e52dca4e539
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-03 08:52:35 +00:00
Patrick Rudolph
4d4953b261 soc/intel: Fix compilation on x86_64 
Change-Id: I18a0c18fe1c64611f95bc423916447c89585db9f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2021-02-03 08:40:46 +00:00
Felix Held
1254e370cc soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code 
commit 3f2467032e changed this in the APCI
code itself, but the change in the ACPI byte code generation in
pcie_gpp.c was missed and this patch fixes that.

TEST=Fixes the regression on Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60de29581296101947336f70343d6206af97e307
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-02 23:45:45 +00:00
Felix Held
a7f018a00d soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines 
This define was copied over from Stoneyridge, but isn't present on
Picasso and newer.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-02 22:50:35 +00:00
Jakub Czapiga
eb6f80d049 tests: Add lib/region_file-test test case 
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ic48e52a97b18d55fd983315f25dc972f472cc473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-02-02 18:05:26 +00:00
Michael Niewöhner
5ff17ed393 mb/siemens/mc_apl1: do UART pad configuration at board-level 
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49442
Tested-by: siemens-bot
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-02 17:11:42 +00:00
Kyösti Mälkki
d06f800cf8 soc/intel/baytrail,braswell: Drop TOLM from GNVS 
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.

Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50121
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-02 14:50:38 +00:00
Kyösti Mälkki
639cc9c6ba soc/intel/baytrail,braswell: Sync PCI memory region in ASL 
Baytrail had (only) occurence of DwordMemory vs DWordMemory.
Braswell one had bogus comments about the PCI memory range.

The actual region details are dynamically filled in _CRS.

Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-02 14:50:01 +00:00
Elyes HAOUAS
00b5f53361 treewide [Kconfig]: Remove useless comment 
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-02 13:49:49 +00:00
Kyösti Mälkki
060ae5c88b soc/amd/common: Use only byte access for old GPIO 
Change-Id: I06ec29845d051d9b90ab6f3cfb269ad5e6b75ea8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-01 22:43:32 +00:00
Elyes HAOUAS
38fa9f25ee soc/amd/picasso/fch.c: Remove unused <acpi/acpi_pm.h> 
Change-Id: I5fea31f5893227a3e076c83a1759d3795b68c943
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-01 17:44:23 +00:00
Kyösti Mälkki
ea1dd2e7a8 soc/amd/common: Drop ACPIMMIO GPIO bank separation 
It's assumed in ASL already that the banks appear one
after other in ACPIMMIO space. There is no need for
the separation of accessor functions by name.

Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-01 15:21:51 +00:00
Kyösti Mälkki
df84a28ccc mb/pcengines/apu2: Switch to proper GPIO API 
Use the abstractions <gpio.h> provides.

Change-Id: I348ba43a76287be5b24012ae3dfc28ed783da9c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
 2021-02-01 10:33:44 +00:00
Angel Pons
b8a82496fe soc/intel/broadwell/gma.c: Add missing break in switch 
Otherwise, the `GT_CDCLK_675` case falls through and exits early.

Change-Id: Icb979f8a980e1a1e1c712c5d9bc8d94c90376b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-01 09:05:34 +00:00
Yu-Ping Wu
39a84879f5 soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size 
From the output of 'objdump -x dram.elf', the DRAM blob needs 222K
memory, but currently only 208K is reserved for it. Since MT8192 has 1MB
SRAM L2C, increase SRAM_L2C_END to 0x00300000, and reorganize regions in
SRAM_L2C to have larger DRAM_INIT_CODE (256K). The size of
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE is also increased to 252K.

BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Asurada booted successfully
BRANCH=none

Cq-Depend: chrome-internal:3568265
Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
 2021-02-01 09:04:48 +00:00
Angel Pons
3b7983a044 sb/intel/i82801ix: Factor out common acpi_fill_madt 
It is the same for all three mainboards.

Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50027
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-01 09:04:25 +00:00
Angel Pons
cf445ea89b sb/intel/common/rcba.h: Guard RCBAx macro parameters 
Add brackets around the parameters to avoid operation order problems.

Change-Id: I689983b5b937f66b1a520eea61a38fb96c13c007
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50035
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-01 09:03:50 +00:00
Elyes HAOUAS
7d66b39513 soc/intel/skylake/Kconfig: Remove duplicated INTEL_DESCRIPTOR_MODE_CAPABLE 
Change-Id: I15a1c17e870b04cc1238b54e4f69c227c877ca09
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-01 09:03:26 +00:00
Elyes HAOUAS
26c0e95394 src/soc/intel: Remove CPU_INTEL_COMMON_SMM selection 
CPU_INTEL_COMMON_SMM is already selected in cpu/intel/common/Kconfig file.
Also remove duplicated 'CPU_INTEL_COMMON'.

Change-Id: I3328da567ac588e9bf6d57481fca117cc302a23a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-01 09:03:05 +00:00
Elyes HAOUAS
9660f06634 cpu/x86/name/name.c: Clean up includes 
Also sort includes alphabetically.

Change-Id: I49615434b140601ce599b4a63aa42c82874bd0f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-01 09:02:35 +00:00
Elyes HAOUAS
a8817fc05f src: Remove unused <cpu/x86/smm.h> 
Change-Id: Ic3f85a8fbc6a84074f45d94514e1dcfa78cb0958
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-01 09:01:35 +00:00