The EARLY_CONSOLE Kconfig symbol was removed in
commit 48713a1b - console: Drop EARLY_CONSOLE option
The arm64 and mips directories don't even have early_console.c
to include.
Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10615
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kconfig sometimes fails to parse the last line of a file if there's
no newline at the end. Add one to be safe.
Change-Id: Ia9973a89b12596e1f2a2741ad2e255e886495331
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10614
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because Kconfig uses the first valid default that it comes across, the
'source' commands to load sub-Kconfigs should be ordered from the
most specific (mainboards) to less specific (chipsets) to least specific
(architectures). This allows the mainboards to override chipsets and
architecture Kconfig files.
Because the architecture files were getting loaded ahead of the chipset
and cpu Kconfigs, the preferred defaults values for things such as
NUM_IPI_STARTS or RISCV_BOOTBLOCK_CUSTOM could not be set.
Change-Id: Ic327452833f012ec06dabb5b5ef661aba3aff464
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10609
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
buildgcc fails if g++ or clang isn't found on the host. This
was failing on OSX due to the string used to check for clang
doesn't match "Apple LLVM". Add an additional search string for
clang "LLVM".
Change-Id: I05e36cfc690061b3233376d57f44f197cab933ea
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10569
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With this change, the x86_64-elf-gcc can compile i386-elf
binaries by specifying -m32. The patch against GCC is needed
to enable building the 32bit libraries when building x86_64-elf-gcc
Change-Id: Ic86a009eccfdf3e33a398bcdcc13b15c8dfc0d31
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10497
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Adding new board based on AMD Kabini.
Most of the code is copied from gizmosphere/gizmo2
Board is developed by BAP - Bruhnspace Advanced Projects:
http://www.unibap.com/ (Site is under construction)
Special on this board is:
-Soldered down memory
-SuperIO Fintek F81866D
Known bugs:
-S3 doesnt work
-Serial ports only works for the first boot. Needs power cut.
Tested with:
-SeaBios as Payload
-Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1
-Windows 8 64Bit
Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10288
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Provide ACPI devices with devicetree-compatible annotations for the
three leds and the button of the APU1, as well as the GPIO driver.
This will cause the Linux kernel to automatically load the following
modules:
leds_gpio (CONFIG_LEDS_GPIO)
gpio_keys_polled (CONFIG_KEYBOARD_GPIO_POLLED)
gpio_sb8xx (CONFIG_GPIO_SB8XX)
See
http://events.linuxfoundation.org/sites/events/files/slides/ACPI_vs_DT.pdf
and https://lwn.net/Articles/612062/ for some more information on how
the PRP0001 HID works.
To make this usable a Linux GPIO driver for the AMD chipset is also
required, which I am currently working on, but have not submitted
upstream yet.
Leds have been named after the convention in
Documentation/leds/leds-class.txt:
LED Device Naming
=================
Is currently of the form:
"devicename:colour:function"
For comparison, on an OpenWRT device:
GPIOs 0-21, ath79:
gpio-1 (tp-link:green:usb ) out hi
gpio-2 (tp-link:green:system) out lo
gpio-3 (reset ) in hi
gpio-5 (tp-link:green:qss ) out lo
gpio-7 (qss ) in hi
gpio-9 (tp-link:green:wlan ) out lo
gpio-18 (rtl8366rb ) in hi
gpio-19 (rtl8366rb ) in hi
On the apu1:
GPIOs 288-511, platform/PRP0001:00, AMD SB8XX/SB9XX/A5X/A8X GPIO driver:
gpio-475 (switch1 ) in hi
gpio-477 (apu1:green:led1 ) out hi
gpio-478 (apu1:green:led2 ) out hi
gpio-479 (apu1:green:led3 ) out hi
Change-Id: I956ee92d9d98ef27a83ccb30d314543bd8634f2c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10540
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch checks for following conditions
(1) while enabling LTR, if PCI_CAP_ID_PCIE is don't found
then don't enable LTR.
(2)
2.1) set_L1_ss_latency is member if ops_pci, which could be NULL.
so confirm ops_pci is not NULL before calling its member function.
2.2) if PCI_CAP_ID_PCIE is not found, then don't try to set latency.
BUG=none
BRANCH=none
TEST=build and boot coreboot with L1 substate enabled on sklrvp3.
Change-Id: I31965266f81f2a12ee719f69ed9a20b096c8b315
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3592a7c974186f2f1113cb002db4632c8f1ab181
Original-Change-Id: I95041490f9fafd2d6f57a8279614ccb7994a1447
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/10559
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This CL is in preparing for tegra mtc that is invoked by dev init.
mtc currently requires floating point instructions support.
BUG=chrome-os-partner:40999
BRANCH=none
TEST=Build and boot smaug
Change-Id: I470dfcd86026812d617f9ff4f4fcdce601195857
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e3f7336fc7cedf96dab4eff204616519856f831
Original-Change-Id: I14c0003ce76ddf4b4ebb0cf171ea3c62cab55ef9
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/275112
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
When required tools are missing, try to give the user more detailed
information on how to solve the problem.
Change-Id: Ifa21c1af38a036a7d4f5a786041a87a7d45f4ec5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10555
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This moves the CMAKE definition down into the case statement
for $PACKAGE so that it is only required when the user wants to
build clang.
With this approach, "./buildgcc -P clang" will error out with the
"ERROR: Missing tool:" message if cmake is not installed.
Change-Id: I1e5c1bd67ade8f93ba0390df7f234deb47b9b18a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/10556
Tested-by: build bot (Jenkins)
Reviewed-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Almost all of the code between x86 and x64 can be shared, so select it for
either architecture.
Change-Id: I681149ed7698c08b702bb19f074f369699cef1bf
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8693
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For now, share code with x86, and use the "large" code model.
Also align the architecture specific CFLAGS in toolchain.inc
for cosmetics.
Change-Id: Ie84893d3460115802fbd70c28b10e709029c6b4e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The smbus.asl operation regions prevent the Linux i2c driver (i2c_piix4)
for this chipset from claiming the ioport ranges and thus it fails to
load.
The methods defined in smbus.asl are not used in the DSDT and also don't
exist in the DSDT of the vendor firmware.
In particular due to the following check in i2c-piix4.c will fail unless
acpi_enforce_resources=no is explicitly set on the Linux kernel
parameters:
if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
return -ENODEV;
Depending on kernel options the only error message printed is
ACPI Warning: SystemIO range 0x0000000000000B00-0x0000000000000B07 conflicts with OpRegion 0x0000000000000B00-0x0000000000000B0B (\SMB0) (20150410/utaddress-254)
ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
However since it does not implement a standard interface there is no
native ACPI driver for smbus.asl.
Change-Id: Id8401e8b36f0e2412d490a92c20540a04d853125
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10539
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The same values are used on my Lenovo R400 as reported by Francis Rowe
from his T400 and T500.
TEST: Read /proc/asound/card0/codec#0, see that the jack locations
correspond to the board layout, e.g. headphone and microphone
connectors are on front of the laptop, not right. Read
/sys/class/sound/hwC0D0/init_pin_configs, see that it has the same
content as with factory firmware.
Change-Id: I60e914ca9fab4bb2c99b4ed9e6d81a0580a88b18
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Reviewed-on: http://review.coreboot.org/10431
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Commit 8d80a3fb (ASRock DSDT: Split the ASRock DSDT) creates the file
`acpi/smbus.asl` in the board directory, but includes the identical
southbridge file in `dsdt.asl`.
So, the file is actually unused. Therefore remove it.
Change-Id: I26c5a2eaf3822d37da2402da65b278a3ee6d42f0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10544
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of having three copies of amdlib, the glue code for Agesa,
let's share the code between all implementations (and come up with
a versioned API if needed at some point in the future)
Change-Id: I38edffd1bbb04785765d20ca30908a1101c0dda0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10507
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Add all of the PI source that will remain part of coreboot to
build with a binary AGESA PI BLOB. This includes the gcc makefiles,
some Kconfig, and the AGESA standard library functions.
Change vendorcode Makefile and Kconfig so that they can compile
AMD library files and use headers from outside the coreboot/src
tree.
Change-Id: Iad26689292eb123d735023dd29ef3d47396076ea
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10416
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
