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Author SHA1 Message Date
Anil Kumar
c6f5b05cf3 mb/google/deltaur: Return SKU ID info 
For Deltaur and Deltan variants return proper SKU ID based on EC
firmware type and sensor detect GPIO value

BUG=b:152544516
TEST=make build successful for deltan

Change-Id: I20a497739e5062400b093648c3a634203dec6105
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2020-04-13 20:26:54 +00:00
Varun Joshi
06684979f9 mb/google/deltaur: Update onboard memory config 
Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.

BUG=b:151702387

Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-04-13 20:24:59 +00:00
Rajat Jain
3639f38171 include/input-event-codes.h: Add Linux input key codes header file 
Add header file from keycodes from Linux sources. This is needed so
that coreboot can provide scancode to keycode mappings in the ACPI
that the linux kernel expects (https://lkml.org/lkml/2020/3/24/588)

Signed-off-by: Rajat Jain <rajatja@google.com>
Change-Id: I40051cb63a6c154728887ac9b0521bc671b2a518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40029
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-13 19:54:30 +00:00
Rajat Jain
999001144f util/lint: Accept "GPL-2.0-only WITH Linux-syscall-note" licenses 
The Linux kernel UAPI header files are licensed under
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */

Allows files with this license to be included in coreboot.
For more details about this particular license:

https://www.kernel.org/doc/html/v4.17/process/license-rules.html
https://spdx.org/licenses/Linux-syscall-note.html

Change-Id: I4f0f8d36c637a66a6999a18321fdbc4c42d5751e
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-04-13 19:54:19 +00:00
Srinidhi N Kaushik
3907a64a48 mb/google/volteer: enable Early Command Training 
Update memory configuration on Tiger Lake platform to enable Early
Command Training. This feature was not supported before FSP v2527.

BUG=b:150357377
BRANCH=None
TEST= Build and boot volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I674c30f4dfc1af6c0c4a460d66684545a190caf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40023
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-13 15:51:01 +00:00
Aaron Durbin
4ed96f2443 ec/google/chromeec: add smbios_mainboard_manufacturer() 
When EC_GOOGLE_CHROMEEC_SKUID is selected provide an
implementation of smbios_mainboard_manufacturer() so the code
doesn't need to be duplicated in the mainboards.

BUG=b:153767369

Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-04-13 15:03:48 +00:00
Marshall Dawson
d2d93829bb cpu/x86/smm.h: Add SW SMI for PSP SMM Info 
Add a definition for a software SMI to allow AMD systems supporting
the MboxBiosCmdSmmInfo command to properly initialize the PSP.

BUG=b:153677737

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I1d78aabb75cb76178a3606777d6a11f1e8806d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40294
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-13 12:39:25 +00:00
Marshall Dawson
d6b7236732 soc/amd/common/psp: Split mailbox support into v1 and v2 
Family 17h redefines the PSP command and status, and therefore the
steps required to send commands via the mailbox.  Convert the existing
version into a v1 and add a v2.  New Kconfig options allow the soc to
choose v1 vs. v2.

The v2 PSP begins responding to the mailbox command when the full
bit range is written.  Define the new mailbox as a union of a u32
and a structure.

Additional PSP details may be found in the NDA publication (#55758)
  AMD Platform Security Processor BIOS Architecture Design Guide for
  AMD Family 17h Processors

Change the existing two soc functions that return pointers to void
pointers.

BUG=b:153677737

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4d358fdae07da471640856f57568059e9487f6a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-13 12:39:12 +00:00
Felix Held
a67c753d55 soc/amd/picasso/soc_util: add TODO to Dali detection 
Change-Id: I8ff5a9275d4cdf0049b63cc30b8a1cc376b50f80
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-13 12:38:30 +00:00
Ronak Kanabar
da968d5f2e mb/intel/jasperlake_rvp: Enable S0ix for JSLRVP 
Enable S0ix from devicetree for JSLRVP

TEST= Build, boot JSLRVP and Verified S0ix is
working by running "echo freeze > /sys/power/state"
from kernel console.

Change-Id: Iedbd7ce9db546f8dc6cb3343fa624abde0ef0d3f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
 2020-04-13 06:45:10 +00:00
Maulik V Vaghela
d7564dc1b9 mb/intel/jasperlake_rvp: Enable audio 
Enable audio for Jasper Lake RVP board. It has 2 Audio codec chips
connected on I2C0: DA7219 and MAX98373

1. Enable Kconfig to enable I2C drivers for both chips.
2. Make necessary devicetree changes to enable FSP UPDs and ACPI entry
   for I2C0.
3. Enable audio related GPIO configurations.

BUG=None
BRANCH=None
TEST=Checked that dmic and speaker are functional on Jasper Lake RVP

Change-Id: Ibf76eb36c478bd33cbc0c86099236452b397fcc5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39695
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-13 06:44:51 +00:00
Aamir Bohra
9225fd5040 soc/intel/tigerlake: Remove scs.asl 
Remove EMMC and SD card ACPI devices copied from Ice Lake.
Tiger Lake does not support these controllers.

BUG=b:151208782
TEST= Build volteer board

Change-Id: I4b3e37f93b94757d16d775fb27bee644d9dc539e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40228
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-13 05:44:44 +00:00
Srinidhi N Kaushik
9a90a439a2 soc/intel/tigerlake: Disable MrcSafeConfig 
This change disables MrcSafeConfig option during MRC training.
MrcSafeConfig was enabled as part of the early testing.
Now with FSP 2527, there is no need to set this config anymore.

BUG=b:150357377
BRANCH=master
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-11 21:31:54 +00:00
Srinidhi N Kaushik
083379d0f8 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527 
Update FSP headers for Tiger Lake platform generated based FSP
version 2527. Which includes below additional UPDs:

FSPM:
 - PchTraceHubMode
 - CpuTraceHubMode
 - CpuPcieRpEnableMask
FSPS:
 - D3HotEnable
 - D3ColdEnable
 - RtcMemoryLock
 - PchLockDownGlobalSmi
 - PchLockDownBiosInterface
 - PchUnlockGpioPads
 - CpuMpPpi
 - ThcPort0Assignment
 - ThcPort1Assignment

BUG=b:150357377
BRANCH=none
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-11 20:28:26 +00:00
Aaron Durbin
32107dffb7 ec/google/chromeec: expose failure and unprovisioned SKU id values 
Provide CROS_SKU_UNKNOWN and CROS_SKU_UNPROVISIONED defintion so
callers can utilize the default and failing value without open coding it.

BUG=b:153642124

Change-Id: I447004e9016b6ab3306ea532721494ebbcda741d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40299
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-11 14:26:47 +00:00
Scott Chao
2a203c50ef mb/google/kukui: correct board name 
Modify board name from "Kadadu" to "Kakadu"

BUG=b:153590144
TEST=CPU log show "Starting depthcharge on Kakadu..."
BRANCH=kukui

Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Change-Id: Ibf387b0e0153315ff2ab5c19381db44a61c14e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40283
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-11 09:32:42 +00:00
Elyes HAOUAS
3dff32c804 nb/i945: Improve code formatting 
Change-Id: I8a1eadcdc51dedd1e17eb6ae7847d9209b2bd598
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-11 09:19:13 +00:00
Elyes HAOUAS
fd8de1860d src/mb: Remove unneeded spaces before/after tabs 
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-10 22:30:06 +00:00
Jake Mannens
a0722870a8 mb/lenovo/t420s/devicetree.cb: Fix PCIe port definitions 
The NEC uPD720200A USB 3.0 controller on the T420s is actually
connected to PCIe root port #5 on the PCH, not #7. Enable RP#5,
disable RP#7 and update comments accordingly.
Test=USB 3.0 controller shows in `lspci`

Change-Id: I21ac72fd5632e552bdcdbd573cf92b433ed545ff
Signed-off-by: Jake Mannens <jakem_5@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-04-10 22:28:00 +00:00
Aamir Bohra
cf0d1c3164 soc/intel/jasperlake: Publish EMMC and SD card ACPI devices 
BUG=b:150872580
TEST=Build waddledoo board. Verify EMMC and SD card ACPI devices are
     present in dsdt.asl.

Change-Id: I70d47455c48990afe9e79c013c5272d70f4f71e7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2020-04-10 19:33:23 +00:00
Karthikeyan Ramasubramanian
d38108f26f mb/google/dedede: Add Synaptics Touchpad configuration for waddledee 
TEST=Build and boot the mainboard. Ensure that the touchpad is
operational.

Change-Id: I937462cd3992a884194bbd1759a0802a147e925a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-04-10 19:32:59 +00:00
Aamir Bohra
30ab312322 soc/intel/jasperlake: Publish single GPIO ACPI device 
Current pin-ctrl kernel v5.4 driver expects the firmware to publish
single GPIO ACPI device. Until kernel pin-ctrl driver implementation is
updated to consume community based GPIO ACPI device, update the current
ACPI code to comply with pin-ctrl driver requirement.

BUG=b:150154277
TEST=Verify intel pin-ctrl driver can successfully load in OS

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: Ifcc92adaee550182ab405541ea85019f31bb8658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2020-04-10 19:31:48 +00:00
Karthikeyan Ramasubramanian
e9eb4d5df9 mb/google/dedede: Add weak pull-up for EC_AP_PWR_BTN_ODL gpio 
According to the EDS, EC_AP_PWR_BTN_ODL has a default internal pull-up
of 20K. Retain it during the GPIO pad configuration.

BUG=b:150985246
TEST=Boot the mainboard.

Change-Id: I042ba70f78fca1a5b9eda30029df97b3f8e65656
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39852
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-10 19:31:18 +00:00
Morgan Jang
ea9787a6b2 drivers/ipmi: Implement the function for logging system events into BMC 
Implemented for functions that need to log system events into BMC,
the information of system events can be specific.

TEST=Use ipmitool and execute "ipmitool sel list" command to check
     if SEL is added into BMC.

Change-Id: I38f3acb958d12c196d33d34fd5cfa0b784f403b7
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-04-10 18:08:02 +00:00
Scott Chao
e6d1c7fae8 spi: add Winbond W25Q64JW spi rom support 
BUG=b:153515968
TEST=Able to boot to kernel

Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com>
Change-Id: I699f6d7ba3af01436f10c9a59af4a22fc45aa300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40270
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-10 15:14:53 +00:00
Elyes HAOUAS
4d319c3d09 src/ec: Add missing "set_resources = noop_set_resources" 
Change-Id: I4acfb9d9911e251a494b6d35d76226c06e7858d6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-10 12:00:11 +00:00
Elyes HAOUAS
7eed98ac88 util/nvramtool: Remove 2nd initialization 
'result' is already defined as 'unsigned long long result = 0;' so no
need to re-write 'result = 0;'.

Change-Id: Ie897453fb5e7b09af755ce8d61ee8e80943ffc1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-04-10 11:56:13 +00:00
Nico Huber
2f8ba69b0e Replace DEVICE_NOOP with noop_(set|read)_resources 
`.read_resources` and `.set_resources` are the only two device
operations that are considered mandatory. Other function pointers
can be left NULL. Having dedicated no-op implementations for the
two mandatory fields should stop the leaking of no-op pointers to
other fields.

Change-Id: I6469a7568dc24317c95e238749d878e798b0a362
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-10 11:50:22 +00:00
Nico Huber
a461b694a6 Drop unnecessary DEVICE_NOOP entries 
Providing an explicit no-op function pointer is only necessary for
`.read_resources` and `.set_resources`. All other device-operation
pointers are optional and can be NULL.

Change-Id: I3d139f7be86180558cabec04b8566873062e33be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-10 11:25:04 +00:00
Varun Joshi
9734325f45 soc/intel/tigerlake: Add support to initialize DDR4 Memory 
Support to configure DDR4 memory variant.
	-Add support to read SPD data based on different memory topology.
	-Initialize FSP UPD's for DQ and DQS mapping.

BUG=b:151702387

Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39847
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-10 01:57:27 +00:00
Elyes HAOUAS
c2e796290a mb/*/*/hda_verb.c: Improve code formatting 
Change-Id: I294ea867678ad77e454873ecf4948bf2d12c9f80
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-10 00:13:12 +00:00
Nico Huber
db2c8dfecb assert.h: Simplify dead_code() 
It turns out the linker's error message already includes the line
number of the dead_code() invocation. If we don't include the line
number in the identifier for our undefined reference, we don't need
individual identifiers at all and can work with a single, global
declaration.

Change-Id: Ib63868ce3114c3f839867a3bfb1b03bdb6facf16
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-10 00:10:58 +00:00
Elyes HAOUAS
17419ff948 mb/intel/icelake_rvp/variants/icl_u: Improve code formatting 
Change-Id: I2a87e5c0f598d665f1c64ac8cfe235918326d1d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 23:49:47 +00:00
Elyes HAOUAS
3408a0ef0c mb/intel/d945gclf: Improve code formatting of devicetree 
Change-Id: I3c8d430a10562edd4404d322e78f603cae191026
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 23:49:12 +00:00
Evgeny Zinoviev
408fdeba7f Doc/mb/lenovo/ivb_internal_flashing: Fix a typo 
unmount -> umount. My mistake.

Change-Id: I5d1b675f6ab7c027f2e646424adb1f255967c753
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 23:44:21 +00:00
Christian Walter
b2f8ce7591 soc/intel/cannonlake: Steal no memory for disabled IGD 
Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct'
to do it like this, otherwise the FSP would always allocate memory for
the IGD even if it is disabled. In addition the FSP enables the graphics
panel power even if no IGD is present which leads to a crashing FSP.
Thus, if no IGD is present we switch off the panel via UPDs.

Refer to this issue on IntelFSP for details:
https://github.com/IntelFsp/FSP/issues/49

Tested on:
* CFL platform with IGD
* CFL platform without IGD

Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2020-04-09 21:49:01 +00:00
Matt DeVillier
6670f44cd0 payloads/nvramcui: Select USE_OPTION_TABLE 
nvramcui requires use of CMOS for NVRAM configuration,
so depend on HAVE_OPTION_TABLE and select USE_OPTION_TABLE
to ensure that nvramcui is actually functional when included
in a build.

Change-Id: I0595514f636b8ce67bbc789ecc96a93c99068c50
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 15:27:30 +00:00
Furquan Shaikh
a6cf8d6465 ec/google/chromeec: Replace uses of ec_current_image with ec_image 
This change replaces all uses of ec_current_image with ec_image since
Chromium OS EC has deprecated (sha 78d1ed61d) the use of enum
ec_current_image and instead changed it to enum ec_image.

BUG=b:149987779

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7e45ea6c736b44040561f0f8a80f817ade8db864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-04-09 15:10:33 +00:00
Furquan Shaikh
e6c04b9255 ec/google/chromeec: Update ec_commands.h 
This change copies ec_commands.h directly from Chromium OS EC repo at
sha b3c3f6a8f.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I940f5c7fe8ad4d989a1dfcd6da3ccf9fc151ec56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-04-09 15:09:45 +00:00
Elyes HAOUAS
a895c32242 soc/intel: Remove unneeded whitespaces 
Change-Id: Ib156ebede1ee24a1c7bd20d01792ec80cba8f37d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 14:51:41 +00:00
Elyes HAOUAS
af0f410c70 drivers/intel/gma: Remove unneeded white space 
Change-Id: I816cfe0e3114fe270c6c48014705dbee3b10fd50
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 14:48:31 +00:00
Elyes HAOUAS
961658f3dc nb/intel/i945: Use 'const' to set pci_devfn_t statically 
Change-Id: I879dd2fc61bc385486b506e2123f32629a67f518
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 14:45:38 +00:00
Elyes HAOUAS
eb00e8722b sb/intel/i82801gx: Use 'const' to set pci_devfn_t statically 
Change-Id: I4b33b42f41c7e34c5eab70edf2f12862816220d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 14:43:57 +00:00
Elyes HAOUAS
25d20d3332 sb/{bd82x6x,ibexpeak,lynxpoint}/early_smbus: Use macro 
Change-Id: If57d785b92f0f09d9def90b8ac87833321e3cfcf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 14:42:56 +00:00
Edward O'Callaghan
200f02a518 mb/google/hatch: Allow variants to not necessarily be laptops 
In some cases Hatch variants are not laptop form-factors such
as Puff. Ensure that the base configuration does not assume
the form factor and allow variants to elect their intended
use-case.

Note that the issue is that early ec sync needs to be
disabled for EFS2 to function correctly, see commit 6daa8c3ba5
from the FIXME line. The relationship is that desktops do not
have a battery.

BUG=b:152951181
BRANCH=none
TEST=none

Change-Id: I15dc9efa51e9d61297868df287879dfb62909e33
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40252
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-09 13:43:33 +00:00
Felix Singer
ef6eceea56 sb/ibexpeak: Use .device for single PCI ID 
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I40c4447579cfbf2b9c52dcfaa34f34b22f75c89c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39332
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-09 10:52:52 +00:00
Arthur Heymans
dc98bed869 mb/intel/d510mo: Add vbt file 
Add vbt file extracted from the vendor UEFI blob version 0524.

Change-Id: Idd39065e9cf5a420317d79695cf032713173eeab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-09 08:51:51 +00:00
Felix Held
00058f513e soc/amd/picasso: replace get_soc_config with config_of_soc 
get_soc_config was a reimplementation of config_of_soc, so drop
get_soc_config and cfg_util.c.

Change-Id: I007c83cfe5063130c18819925844b6c643cf0232
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-08 21:45:11 +00:00
Felix Held
72e987d540 soc/amd/stoneyridge: replace get_soc_config with config_of_soc 
get_soc_config was a reimplementation of config_of_soc.

Change-Id: I73c6a84703e22d6778b830f4bb82419361c85ff7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2020-04-08 17:15:23 +00:00
Seunghwan Kim
e0b41fd12e mb/google/nightfury: Update DPTF parameters 
Apply initial DPTF parameters for nightfury from internal thermal team. Will update after further thermal/performance tuning.

BUG=b:149226871
BRANCH=firmware-hatch-12672.B
TEST=built and verified FAN worked by DPTF active policy

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I712bdd8edc999ef7ee33f4adf21893be12e86bec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-04-07 23:18:26 +00:00