1 Commits

Author SHA1 Message Date
Lijian Zhao
7673f2f5e9 soc/intel/cannonlake: Add ramstage uart debug support
Use fixed resources for LPSS uart devices for debugging purpose.

BUG=NONE
BRANCH=NONE
TEST=Boot up with coreboot rom, without this changes, serial log will
stop print anything during PCI resourcre setup as MMIO address of UART
will be re-assigned.

Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13 17:25:02 +00:00