AMD Firmware tool allows configuring the directory table level in which
the binaries have to be added. This helps to achieve space and boot time
savings.
BUG=b:195329409
TEST=Build and boot to OS in Guybrush. Achieve a boot time savings of
~75 ms and space savings of ~600 KB per RW section.
Change-Id: Idc212b8c4f8aacfb0132983a8055f1e97af42983
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
When the entry delay of L0s is less than the entry delay of L1, GL9755
will enter L0s state first. When it exits from L0s state, the time of L1
entry will be reset. Therefore, the conditions for entering L1 state
cannot be met. In order to enter L1 state, L0s needs to be disabled.
BUG=b:195611000
TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since the binaryPI glue code is specific to a binary interface, but not
for a hardware block, move it out of the common blocks directory. This
also brings the binaryPI support in line with the FSP support which is
used on the newer generations. This also drops the
SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already
existing SOC_AMD_PI Kconfig option instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I014e538f2772938031950475e456cc40dd05d74c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The code in soc/amd/common/block/s3 is specific to the AMD binaryPI
coreboot integration, so move the code to soc/amd/common/block/pi. This
drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the
dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig
option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not
SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking
process, we don't lose support for any working configuration by only
having one Kconfig option for both parts.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use the same function name as in soc/intel for this functionality. This
also brings the function name more in line with the extended version of
this function gpio_configure_pads_with_override which additionally
supports passing a GPIO override configuration.
This might cause some pain for out-of-tree boards, but at some point
this should be made more consistent, so I don't see a too strong reason
not to do this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The variant creation script creates a placeholder file called
mem_parts_used.txt, with the intent that variant owners will populate
this file with memory parts as needed. But instead, some partners have
been adding the parts in a new file called mem_list_variant.txt and
removing the placeholder file. E.g. https://review.coreboot.org/55735.
There's nothing wrong with this, but it's confusing to have two
different file names which serve the same purpose. Bulk rename all the
mem_list_variant.txt files to mem_parts_used.txt. The only time these
file names are used is as an argument to the spd_tools part_id_gen
script, so no other changes are necessary.
BUG=None
TEST=Re-run part_id_gen for all variants of
brya/volteer/dedede/guybrush/zork. Check that the only change is to the
"Generated by" comment in Makefile.inc and dram_id.generated.txt.
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Icdeee78ae5c01e97f66c759c127175b4962d5635
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The copano and collis variants have both a mem_parts_used.txt and a
mem_list_variant.txt. The mem_parts_used.txt files are empty, so delete
them.
BUG=None
TEST=None
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ia98aad7238b0173b8d5c048d89637bc297d02283
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all zork variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for dalboz:
util/spd_tools/bin/part_id_gen \
PCO \
ddr4 \
src/mainboard/google/zork/variants/dalboz/spd \
src/mainboard/google/zork/variants/dalboz/spd/mem_parts_used.txt
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/zork -a -x --timeless
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I305a24f9345bab28ff35e317b6e7fd7efba22413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57772
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is another gpio group, namely HVCMOS, between GPP_C and GPP_E. Add
it, so the group index calculation for GPI/SMI/NMI results in the
correct value.
Reference: Linux linux/drivers/pinctrl/intel/pinctrl-icelake.c
Change-Id: I7725191173ddc0d43bbe940cdf3b0dc2aa3e5f8d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The moonbuggy pcie topology is the same as genesis so copy from its
device tree and gpios in order to enable these devices.
BUG=b:199746414
TEST=lspci
Change-Id: I4e916a95047b9f955734f164d7578c520478f5af
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This CL uses a 16-bit value (instead of an 8-bit value) for the year.
This is needed because the function internally does a "year % 100", so
the year should not be truncated to 8-bit before applying the modulo.
This fixes a regression introduced in commit e929a75.
BUG=b:200538760
TEST=deployed coreboot. Manually verified that year is correct using
"elogtool list"
TEST=test_that -b $BOARD $DUT firmware_EventLog
Change-Id: I17578ff99af5b31b216ac53c22e53b1b70df5084
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all guybrush variants
to use this new location. The contents of the new SPDs are identical,
only their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for guybrush:
util/spd_tools/bin/part_id_gen \
CZN \
lp4x \
src/mainboard/google/guybrush/variants/guybrush/memory \
src/mainboard/google/guybrush/variants/guybrush/memory/mem_list_variant.txt
For dewatt, the Makefile.inc was manually modified to use the new
placeholder value.
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/guybrush -a -x --timeless
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I48ca430b80b892d68dad582b1d9937a9edafa5d4
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all dedede variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for cret:
util/spd_tools/bin/part_id_gen \
JSL \
lp4x \
src/mainboard/google/dedede/variants/cret/memory \
src/mainboard/google/dedede/variants/cret/memory/mem_parts_used.txt
For cappy, the Makefile.inc was manually modified to use the new
placeholder value.
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/dedede -a -x --timeless
Change-Id: I2871ff45d6202520d4466b68a4d5bb283faf2b63
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently, trying to regenerate the galtic Makefile.inc and
dram_id.generated.txt using part_id_gen fails due to duplicate fixed IDs
in the mem_parts_used.txt file.
Remove the fixed IDs since they aren't needed. The part IDs assigned are
the same either way.
Also delete the comments from mem_parts_used.txt, since lp4x/gen_part_id
currently doesn't support comments.
BUG=b:191776301
Regenerate the Makefile.inc and dram_id.generated.txt using gen_part_id,
and check that the part IDs don't changed. Command used:
util/spd_tools/lp4x/gen_part_id \
src/soc/intel/jasperlake/spd \
src/mainboard/google/dedede/variants/galtic/memory \
src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ida83814b2f19b4a56eb9fde5939fa6c7874803c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all volteer variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for voema:
util/spd_tools/bin/part_id_gen \
TGL \
lp4x \
src/mainboard/google/volteer/variants/voema/memory \
src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/volteer -a -x --timeless
Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all brya variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.
The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for anahera:
util/spd_tools/bin/part_id_gen \
ADL \
lp4x \
src/mainboard/google/brya/variants/anahera/memory \
src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt
BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using: abuild -p none -t google/brya -a -x --timeless
Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When a new variant is created, it needs to have a path to its SPD binary
defined. Currently, this is done by setting SPD_SOURCES to a placeholder
SPD file, which just contains zero bytes.
To remove the need for a placeholder file, automatically generate a
single-byte spd.bin in lib/Makefile.inc when SPD_SOURCES is set to the
marker value 'placeholder'.
BUG=b:191776301
TEST=Change cappy/memory/Makefile to `SPD_SOURCES = placeholder`. Build
and check that spd.bin contains a single zero byte.
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I11f8f9b7ea3bc32aa5c7a617558572a5c1c74c72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Before this patch, gpio_configure_pads_with_override called
program_gpios once for each GPIO that needed to be configured which
resulted in base_num_pads - 1 unneeded master_switch_set/
master_switch_clr sequences for the gpio_configure_pads_with_override
call. Instead implement gpio_configure_pads_with_override as the more
generic function and program_gpios as a special case of that which
passes an empty override configuration and override pad number to
gpio_configure_pads_with_override.
TEST=GPIO configuration and multiplexer register values are the same for
all GPIOs on google/guybrush right before jumping to the payload before
and after the patch.
Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Earlier generation platform used `HeciEnabled` chip config (set to 0)
and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at
the end of the post. `HeciEnabled` chip config remains enabled in all
latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig
selection from SoC Kconfig as CSE remains default enabled.
BUG=b:200644229
TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device
is listed with `lspci`.
Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
