Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.
Alder Lake is not yet complete, so it has been skipped for now.
Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add code to generate p-state and c-state SSDT objects to coreboot.
Publish objects generated in native coreboot, rather than the ones
created by FSP binary.
BUG=b:155307433
TEST=Boot morphius to shell and extract and compare objects created in
coreboot with tables generated by FSP. Confirm they are equivalent.
BRANCH=Zork
Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
It primarily contains definitions for MMIO windows. Also, remove
includes from files not directly using the definitions it contains.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: Id28080d9b2924463dd3720492d5e717d65fa0071
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45419
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the boldar variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
Add "memory/Makefile.inc" generated by gen_part_id.go
BUG=b:162202257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_BOLDAR
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I92b4b917448d8e5e9176cb983adf7b209956d2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0
syntax across CNL, ICL, JSL, SKL.
TEST=Able to build and boot Hatch, EVE and ICLRVP platform.
Dump and disassemble DSDT to ensure GRXS,GTXS etc functions
implementation remain unchanged prior and after this CL.
Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin
of some CA PIN window is too small than others. Need to enable the CA
perbit mechanism to avoid those risks.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clevo mainboards can be grouped by their common platform. Therefore,
restructure the mainboard directory as a first step, so that the variant
mechanism is used.
This moves most of the code into the variant dir, since the L140CU is
the only variant at the moment.
Change-Id: I9ad1c06f9db854cac1dd420c53dc0c9f010ed716
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45664
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.
BUG=b:169045123
TEST=Verifed CnviBtCore and CnviBtAudioOffload settings and FSP
configuration. Booted up to kernel on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1780da0824d145a79743d5cffdea4821236d4f74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naveen M <naveen.m@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Previously, SMBUS support was not required for Apollo Lake, since the
SPD was read inside FSP-M, during memory initialization. However, the
Kontron mAL-10 COMe module contains Nuvoton HWM chip that is connected
to the processor via SMBUS. This patch adds SMBUS common driver support
for Apollo Lake to initialize this HWM.
TEST = After loading the nct7802 module on the Kontron mAL-10 with Linux
OS, we can read the hwm registers, see temperature and fan speed:
coretemp-isa-0000
Adapter: ISA adapter
Package id 0: +52.0°C (high = +110.0°C, crit = +110.0°C)
Core 0: +52.0°C (high = +110.0°C, crit = +110.0°C)
Core 1: +52.0°C (high = +110.0°C, crit = +110.0°C)
Core 2: +53.0°C (high = +110.0°C, crit = +110.0°C)
Core 3: +53.0°C (high = +110.0°C, crit = +110.0°C)
nct7802-i2c-0-2e
Adapter: SMBus CMI adapter cmi
in0: +3.35 V (min = +0.00 V, max = +4.09 V)
in1: +1.92 V
in3: +1.21 V (min = +0.00 V, max = +2.05 V)
in4: +1.68 V (min = +0.00 V, max = +2.05 V)
fan1: 0 RPM (min = 0 RPM)
fan2: 1729 RPM (min = 0 RPM)
fan3: 0 RPM (min = 0 RPM)
temp1: +53.5°C (low = +0.0°C, high = +85.0°C)
(crit = +100.0°C) sensor = thermistor
temp4: +53.0°C (low = +0.0°C, high = +85.0°C)
(crit = +100.0°C)
temp6: +0.0°C
Change-Id: I408ef84ede27a45fb057e22b2757fa6e66277ddd
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44475
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copy system76/lemp9 to clevo/l140cu, since it's a Clevo notebook
actually and both have the same mainboard.
This commit is meant to create a working copy for clevo/l140cu. The only
changes are names. Further patches will follow to make this mainboard
more generic.
Since system76/lemp9 is based on System76's EC firmware, EC stuff does
not work correctly yet. This will be fixed in another patch.
Tested on TUXEDO InfinityBook S 14 v5 and PCZ Lafité Pro 14.
Change-Id: I7c2993256fd9123a8013df5ba8292ea1ead10f74
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Parse the generated fmap_config.h file instead of the .fmd file supplied
by the board to determine the size and location of the APOB region.
Parsing the generated file allows to write .fmd files without having to
take into account that the shell script part in Picasso's Makefile.inc
can only parse a subset of the .fmd syntax.
BUG=b:157068645
TEST=Timeless build for amd/mandolin resulted in identical binary.
BRANCH=zork
Change-Id: I6ed1903a8157374d78d2865621baa15774d2a7d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45595
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
set DPTC power parameter per clamshell/tablet mode
after EC OP region is accessible.
BUG=b:157943445
BRANCH=zork
TEST=1. emerge-zork coreboot
2. power on DUT in tablet mode then check "thermctl_limit"
will change automatically
Change-Id: Ic3e1119881790c34f5649986334b4e3cecafc02b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Convert gpio.h to a compacter, cleaner format by keeping gpios in a
single line, where possible.
This was done with the following fancy vim regex replacement commands.
(Neither sed, nor awk multiline matching syntax are friends with me...)
Just open src/mainboard/system76/lemp9/gpio.h with vim, type : before
pasting each command, press enter and see how the format changes.
g#^\t//#d
%s/^\t\t/\t/
g/PAD_.*$\n\n[^/]/s/\n//
g#// NC#d
%s#^\t// \(.*\)\n\t// \(.*\)#\t// \1 \2#g
%s#^\t// \(.*\)\n\t\(PAD_.*,\)#\t\2\t\t/* \1 */
%s#^// \(GP.*\)#\t/* ------- GPIO Group \1 ------- */#
Finally some indents and multiline comments need to be fixed manually.
Test: images built with TIMELESS do not differ.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9054274dc4c8942935b6a4789bfc1547dd3d4017
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add new generic helper functions for PSS, PCT, XPSS, objects.
BUG=b:155307433
TEST=Boot Morphius and dump SSDT. Confirm PSS and PCT objects appear
as expected and conform to ACPI_6_3_May16.pdf ACPI specification.
Check XPSS against Microsoft "Extended PSS ACPI Method Specification"
XPSS_spec.doc April 2, 2007.
BRANCH=Zork
Change-Id: I1ea218bcee33093481e82390550ff96d9d2cb8b5
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
