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Author SHA1 Message Date
Angel Pons
2ac4cc6595 sb/intel/common/acpi/pcie.asl: Generalise file comment 
This file is no longer specific to 6 and 7 series PCHs.

Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 22:07:50 +00:00
Angel Pons
f1e81e6eb9 sb/intel/common/acpi/irqlinks.asl: Clean up cosmetics 
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I8562fc3278144380b0ab842d88176114821be823
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46760
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 22:07:28 +00:00
Angel Pons
eeefb022eb soc/intel/broadwell: Use common irqlinks.asl 
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I9179c1b449925cc66628fc3266652b8237ab49e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46759
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 22:06:47 +00:00
Angel Pons
284b39f9c8 soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs 
Commit 2e1f764 (sb/intel/common/acpi/irqlinks.asl: Add missing IRQs)
added these IRQs for Lynx Point and earlier southbridges. Follow suit
for Broadwell, since it also supports them. Vendor firmware of the Asus
X555LAB laptop also contains these IRQs, as per the disassembled DSDT.

Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46758
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 22:03:32 +00:00
Angel Pons
0d8924d880 soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint 
Drop unnecessary smbus.asl in favor of southbridge common code.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.

Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46757
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 22:03:18 +00:00
Angel Pons
f239b5a9f3 nb/intel/haswell: Place CTDP ASL code in a separate scope 
This is just to align the code with what Broadwell does.

Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46756
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 22:03:03 +00:00
Angel Pons
c5381e0f36 nb/intel/haswell/acpi: Align with Broadwell 
Align cosmetics and move CTDP-specific ASL into its own file.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I476a4e01016caa3658177b0fa8916576f4a5e0e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46755
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 22:02:46 +00:00
Matt DeVillier
4727663931 mb/purism/librem_mini: Drop community comments in GPIO config 
These add nothing useful to the GPIO config

Change-Id: Ieecc9bd67d020e141c3a1f1d387034df5e563068
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47190
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 21:22:29 +00:00
Matt DeVillier
aa11f9a826 mb/purism/librem_mini: Update GPIO config 
Update GPIO config using a fresh dump of inteltool from the
vendor (AMI) firmware on a Librem Mini v2, run through intelp2m
with parameters '-p cnl -n -ii'

Change-Id: I747415fb9ab7b21943d256d248729cb9e2b4b945
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47206
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 21:19:19 +00:00
Benjamin Doron
7bb756fad7 util/intelp2m: Update macros 
Change-Id: Ia0a7dea89fdb69e01f0abe577488f26a5d2bd6ed
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 21:14:58 +00:00
Matt DeVillier
0d29bb72a1 mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs 
Change-Id: Id306100fc691dcbde48b65092d0be9d7e73c0722
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47189
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 20:29:21 +00:00
Matt DeVillier
b808e7678d mb/purism/librem_mini: Reorganize devicetree 
Move registers under devices to which they belong.

Change-Id: I61ca7c1db02646252d7421f8b79dfc8a40b2bdb5
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47188
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 20:27:59 +00:00
Matt DeVillier
6e651aaf4e mb/purism/librem_mini: drop unused HeciEnabled register 
this should have been corrected as part of:
commit 3de90d1 [soc/intel/cnl: Set Heci1Disable depending on devicetree config]

Change-Id: I6a103a1de01fc258ef359258a8a64f4c5a181139
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47187
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 20:10:52 +00:00
Matt DeVillier
a41991a3f9 mb/purism/librem_mini: Increase TDP/PL2 setting 
PL2 was set artificially low during development when the active cooling
fan was not functional, and never corrected once the fan was fixed.
Raise PL2 to a value which works with both Librem Mini variants.

Change-Id: Ie377392020f73359aed80ddae727adb6f8d06344
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-11-04 20:10:37 +00:00
Matt DeVillier
0b327a4c3a mb/purism/librem_mini: Drop devicetree settings which default to 0 
All chip registers default to 0, no need to explicitly set them.

Change-Id: I056121170d22393484b0ee79bd0815452161a900
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-11-04 20:10:20 +00:00
Matt DeVillier
40368a29a1 mb/purism/librem_mini: drop SendVrMbxCmd from devicetree 
Not needed for this board.

Change-Id: I15a68b59bc512e571b9590007ea64561b3f3dae1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-11-04 19:44:40 +00:00
Felix Held
d8b36d23fa soc/amd/common/psp: move v1-only mailbox commands to separate section 
Two of the PSP mailbox commands are only applicable to the first
generation of PSP mailbox interface.

Change-Id: Ice940ee780c3d96ae1d9ec7ba49ea4add00e8723
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2020-11-04 19:37:42 +00:00
Arthur Heymans
7f44929ed9 soc/intel/xeon_sp: Add a smm_region function 
This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-04 13:43:09 +00:00
Elyes HAOUAS
0be783b30e mb/samsung/lumpy: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I7ad79a31142af8ae1b62497ade0b4ba7bac3a93c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46214
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:44:33 +00:00
Elyes HAOUAS
b29769a391 mb/ocp/deltalake: Convert to ASL 2.0 syntax 
Generated build/dsdt.dsl files are same.

Change-Id: I5bd8fe629fb969ec14dd400b6463ee1592d6903b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46207
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:44:30 +00:00
Elyes HAOUAS
12f69c5ef1 mb/ocp/tiogapass: Convert to ASL 2.0 syntax 
Generated build/dsdt.dsl files are identical.

Change-Id: Iffd6954dcb3f9fb8bcd89854d84f6944cb520dd1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46208
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:44:26 +00:00
Elyes HAOUAS
38eaf3e13f mb/samsung/stumpy: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are same.

Change-Id: I0eda144f1a4f07ca82b3a799afcd8fc908419e69
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46215
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:44:21 +00:00
Elyes HAOUAS
50fcce54e0 ec/purism/librem: Convert to ASL 2.0 syntax 
Generated build/dsdt.dsl are same for purism Librem 15 v4.

Change-Id: I36cb7a2ebde1161f87e78eeab739b15e3cf88860
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:44:11 +00:00
Elyes HAOUAS
f0334b86dd soc/intel/xeon_sp: Convert to ASL 2.0 syntax 
Change-Id: I43e36f2e736192603be61519d3e185605e81f0e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:43:17 +00:00
Elyes HAOUAS
62a437dd88 mb/roda/rk886ex: Convert *.asl to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I2eea24db6cfd260e0f36243e90a5e01b360f23fb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:43:15 +00:00
Elyes HAOUAS
527690c7bf mb/google/link: Convert to ASL 2.0 syntax 
Generated 'dsdt.dsl' files are identical.

Change-Id: I7d4fc3acd82023b007d80638bcb71476330ef320
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:43:13 +00:00
Elyes HAOUAS
3ed5c9e3cd mb/google/beltino: Convert to ASL 2.0 syntax 
Built google/beltino (Monroe) provides identical 'dsdt.dsl'.

Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:43:09 +00:00
Elyes HAOUAS
29ef574b3f mb/intel/baskingridge: Convert to ASL 2.0 syntax 
Generated 'dsdt.dsl' files are identical.

Change-Id: I5897397bdadf86214ceaf90d8cd706e10969d8c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:42:59 +00:00
David Wu
c98ba03493 mb/google/volteer/var/voema: Update dq/dqs mappings 
Update dq/dqs mappings based on voema schematics.

BUG=b:169356808
BRANCH=volteer
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I1aae4286278e712bf29ebb15738477828d3f74d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-11-04 09:42:28 +00:00
Zheng Bao
3384e4a709 soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION 
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:42:18 +00:00
Zheng Bao
77a2c67dfe amdfwtool: Change all error output to fprintf stderr 
Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:42:04 +00:00
Zheng Bao
9e90807b40 amdfwtool: Add an option to show debug message 
Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2020-11-04 09:41:58 +00:00
Elyes HAOUAS
2f1b51ac2b mb/intel/emeraldlake2: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are identical.

Change-Id: Idd2bf447975b4c9b2cd3b440505c0bd960374165
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:41:27 +00:00
Elyes HAOUAS
e28133a994 mb/getac/p470/acpi: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' are identical.

Change-Id: Ifed93f4b0c360ec74f28926fb7cc9774ae03b8a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:41:17 +00:00
Elyes HAOUAS
50a44350ee mb/getac/p470/acpi/ec.asl: Remove duplicated code 
"If(And(RFDV, 0x02)) {Or(Local0, 0x02, Local0)}" is duplicated.

Change-Id: I91698fb308cd37c65aa65e563bcd88743097f56c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45865
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:41:06 +00:00
Elyes HAOUAS
5f5fd853ed acpi/acpi.h: Update region spaces 
Update operation region spaces according to ACPI Release 6.3 Errata A.

Change-Id: I05305c96a2170eaf651d71ac79b67653745108a2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:40:40 +00:00
Michael Niewöhner
b20aac0721 soc/intel/skl,acpi/acpigen: convert global CPPC package to local one 
Move the global CPPC package \GCPC to the first logical core CP00 and
adapt the reference in the other cores. This is cleaner and avoids
confusion.

Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version

Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-11-04 09:40:21 +00:00
Nico Huber
9e20e2f158 util/qemu: Add comprehensive default config for QEMU Q35 
This config tries to mimic the actual devices of a mainboard
with Intel's Q35 chipset. It provides a much better base to
test coreboot (e.g. its allocator) and payloads.

Change-Id: Id465016e37ee75628a55b9da68facb4ae0efe822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:39:50 +00:00
Nico Huber
a08328ecff util/qemu: Add qemu make target 
Add some mechanics to automatically have a `qemu` make target for
supported configurations. So with a QEMU target selected in Kconfig,
one would ideally only have to run `make qemu` to test things.

There are some notable variables that can be set or adapted in
`Makefile.inc` files, the make command line or the environment.

Primarily for `Makefile.inc` use:
 QEMU-y           the QEMU executable
 QEMU_CFG-y       a QEMU config that sets the available default devices,
                  used to run more comprehensive tests by default,
                  e.g. many more PCI devices

For general use:
 QEMU_ARGS        additional command line arguments (default: -serial stdio)
 QEMU_EXTRA_CFGS  additional config files that can add devices

 QEMU_CFG_ARGS    gathers config file related arguments,
                  can be used to override a default config (QEMU_CFG-y)

Examples:

  $ # Run coreboot's default config with additional command line args
  $ make qemu QEMU_ARGS="-cdrom site-local/grml64-small_2018.12.iso"

  $ # Force QEMU's built-in config
  $ make qemu QEMU_CFG_ARGS=

Change-Id: I658f86e05df416ae09be6d432f9a80f7f71f9f75
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2020-11-04 09:39:11 +00:00
Jacob Garber
6df3870012 soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer 
IIO_RESOURCE_INSTANCE is a large struct, so it should be passed as a
constant pointer rather than making a copy.

Found-by: Coverity CID 1432759
Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46729
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:38:23 +00:00
Patrick Georgi
5193312e1e util/sconfig: Report which key is duplicate 
It slightly helps debugging issues when you know what to look out for.

Change-Id: I21eafaf8291701316aa920e458ba74535121b0a1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-04 09:38:08 +00:00
Arthur Heymans
50526d5a30 mb/emulation/qemu-aarch64: Add a timestamp region 
The romstage region is moved up a bit more to satisfy the MMU.

Change-Id: I00c2b4972495fa669d4dc2a52f298a0e4d0cf5ff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47105
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 09:37:59 +00:00
Jes Klinke
5c7311a524 mb/google/volteer: clang-format mainboard.c 
This CL is entirely generated by running the automatic formatter on this
one file.

BUG=None
TEST=abuild -t GOOGLE_VOLTEER2 -c max -x

Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-04 09:37:42 +00:00
Patrick Rudolph
b5f580e03c mb/prodrive/hermes: Set tcc offset to 1 
Prevent early throttling when the ambient temperature is high.

Change-Id: Ie6881c9c0942aae3e43509170352271a74244d42
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-11-04 09:37:31 +00:00
Arthur Heymans
b38d6bbe1c soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T 
The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size.
FSP-M seems to have a very large stack usage so it would overflow
other car symbols located below the coreboot stack such as timestamps
and the pre-ram console, which are now fixed.

TEST: boot with ocp/deltalake.

Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-04 08:27:31 +00:00
Furquan Shaikh
3cea0594df mb/google/volteer: Log EC events in case of S0ix resume 
This change adds the callback
`elog_gsmi_cb_mainboard_log_wake_source()` to volteer to enable
logging of EC events in case of S0ix resume.

BUG=b:172272078
BRANCH=volteer
TEST=Verified that EC events are logged correctly for S0ix resume:

11 | 2020-11-02 14:11:05 | S0ix Enter
12 | 2020-11-02 14:11:08 | S0ix Exit
13 | 2020-11-02 14:11:08 | Wake Source | Power Button | 0
14 | 2020-11-02 14:11:08 | EC Event | Power Button
15 | 2020-11-02 14:11:17 | S0ix Enter
16 | 2020-11-02 14:11:21 | S0ix Exit
17 | 2020-11-02 14:11:21 | Wake Source | GPE # | 112
18 | 2020-11-02 14:11:21 | EC Event | Lid Open

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7aa9dc2470da3226925927f2a0cc39fdd426e3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47142
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-03 23:58:55 +00:00
Furquan Shaikh
7c36dc12df soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix 
This change adds elog.c to smm-y for Tiger lake and Jasper Lake
platforms to enable the logging of wake sources in eventlog for S0ix.

BUG=b:172272078,b:169731044
BRANCH=volteer
TEST=Verified on volteer that wake sources are correctly logged for
S0ix:
8 | 2020-11-02 13:54:27 | S0ix Enter
9 | 2020-11-02 13:54:33 | S0ix Exit
10 | 2020-11-02 13:54:33 | Wake Source | RTC Alarm | 0
11 | 2020-11-02 13:54:49 | S0ix Enter
12 | 2020-11-02 13:54:54 | S0ix Exit
13 | 2020-11-02 13:54:54 | Wake Source | Power Button | 0
14 | 2020-11-02 13:55:04 | S0ix Enter
15 | 2020-11-02 13:55:10 | S0ix Exit
16 | 2020-11-02 13:55:10 | Wake Source | GPE # | 112

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47141
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-03 23:58:45 +00:00
Angel Pons
1b85692fc4 sb/intel/lynxpoint/sata.c: Don't enable Bus Master 
Bus Master is not required and reference code does not set it.

Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore.

Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2020-11-03 23:40:48 +00:00
Angel Pons
4c2389e28c soc/intel/broadwell: Relocate PCH ACPI files 
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46754
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-03 19:12:35 +00:00
Angel Pons
96a480d507 cpu/intel/haswell: Move smmrelocate.c MSR definitions to header 
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46733
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-03 19:12:01 +00:00