The input buffer to the buffer_to_fifo family of functions is only read,
so it can be a const pointer. (Also, remove the MIPS check in libpayload
for these functions... the MIPS architecture has been removed a while
ago.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
SBI comes with its own memset implementation (under a slightly
different name) that gcc11 "helpfully" tries to replace with a call
to memset(). Since we don't provide a memset, the linker isn't happy,
so prevent gcc from doing that.
Change-Id: I3459a519d46a123f873306000b8b2261bd64e0c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We never call console_init from asm, so we don't need the asmlinkage.
This allows us to remove the arch/cpu.h include since we only needed it
for the asmlinkage #define.
BUG=b:179699789
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9a7895d4f5cba59f6b05915fa4d6c6fd6ab85773
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57568
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that primus can successfully
boot into OS with non-serial coreboot.
BUG=b:199967106
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I9c66efe96515347502d059556052c764c1be5d09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When the century byte was reserved, the debug_level was accidentally
converted from an enum to a hidden value. Change it back to an enum.
Fixes: f05bd8830d ("mb/system76/*: cmos.layout: Reserve century byte")
Change-Id: Id88a7aed7b2fc793fd003db5b45f3f201b1a7630
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
When using a debug build of the FSP, the FSP-M binary is larger than the
memory region we have allocated for it, so increase the size to make the
binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so
that it starts right after the the FSP-M memory region.
TEST=coreboot builds now successfully when using a debug version of the
FSP
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently there are two versions of spd_tools: one for LP4x and one for
DDR4. This change is the first step in unifying these into a single
tool.
This change implements a unified version of the spd_gen tool, by
combining the functionality currently in lp4x/gen_spd.go and
ddr4/gen_spd.go. The unified version takes the memory technology as an
argument, and generates SPD files for all platforms supporting that
technology.
BUG=b:191776301
TEST=Compare the SPDs generated by the old and new versions of the tool
for all supported platforms. For reference, the test script used is
here: https://review.coreboot.org/c/coreboot/+/57511
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I7fc036996dbafbb54e075da0c3ac2ea0886a6db2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
To save the space for FW, some of the FWs are going to be defined as
LVL2 entries. To be compatible to "flattened" layout, we still drop
the LVL2 entry to level1 if there is only one level.
Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators
are connected to the DRAM. With the exception of an early Skylake RVP
board (which doesn't have coreboot support), mainboards using DDR3 or
LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with
DDR4 should set `CaVrefConfig` to 2. MRC uses this information during
memory training, so it is important to use the correct value to avoid
any issues, such as increased power usage, system instability or even
boot failures.
However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2.
Although they can boot successfully, it's not optimal. For boards that
set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2.
Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
vboot_reference is introducing a new field (ctx) to store the current
boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged
in both vboot flow and elog_add_boot_reason in coreboot.
In current steps of deciding bootmode, a function vb2ex_ec_trusted
is required. This function checks gpio EC_IN_RW pin and will return
'trusted' only if EC is not in RW. Therefore, we need to implement
similar utilities in coreboot.
We will deprecate vb2ex_ec_trusted and use the flag,
VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag
in coreboot, verstage_main.
Also add a help function get_ec_is_trusted which needed to be
implemented per mainboard.
BUG=b:177196147, b:181931817
BRANCH=none
TEST=Test on trogdor if manual recovery works
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make neovim the default editor and create an alias for vim.
The NixOS module for neovim is currently broken. Thus, add a note to
`description.md` to switch to that later.
Change-Id: I9345a6e32f3035565e55e50579c97121b4987d83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57393
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Nix shell file which provides an environment for compilation of
the coreboot toolchain. The Nix shell can be used by running the
following command:
$ nix-shell --pure util/nixshell/toolchain.nix
The `--pure` parameter is optional, but it makes sure that the
environment is as minimal as possible and does not contain any unrelated
or unneeded software or configuration.
Once compiled, the coreboot toolchain can be used without loading the
shell environment.
If `--pure` is used, SSL connections won't work since the
`SSL_CERT_FILE` environment variable is not configured, which makes the
build tool unable to download the source files. Thus, let it point to
the system certificate store.
Change-Id: I341ee28c5451d2c6cb4ff22de67161d99f4ca77a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Since the PCIE training for the USB WWAN card is no longer being run,
we can initialize the GPIOs the same for all WWAN cards.
BUG=b:193036827
TEST=Boot and reboot with fibocom FM350-GL & L850GL modules
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57317
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check to see if the PCIe slot needs to be activated for the WWAN card.
If it doesn't, leave it unused so it will be powered off and not do
the PCIe training.
BUG=b:193036827
TEST=Boot & Reboot guybrush with both PCIe & USB WWAN cards.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I79c32e4814672c03ee0821786d5be1c77fd1b410
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:200009010
TEST=ALC5682-VD/ALC5682-VS audio codec can work
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I09c7830fff6b318cf1a1f4a44ee0a819691f7c58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57673
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCIe WWAN module used on brya0 requires control over 4 signals to
successfully power it on. It is desirable to do this before passing
control to the payload, because the modem requires a ~10 seconds
initialization phase before it can be used.
The corrected sequence looks like:
1) Drive device into full reset and enable power in bootblock
2) Deassert FCPO in romstage, after power rails stabilize
3) Deassert WLAN_RST#, then WLAN_PERST# in ramstage
BUG=b:187691798
Change-Id: I10f15a4dcfd86216c334fb24b4693ea250d35ee4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This GPIO is used to force the USB retimers on Type-C ports to stay in a
powered state and can be used e.g., during a firmware update to the
retimer to force power on even when no device may be connected to the
port. However, its power rail is controlled elsewhere and coreboot is
not applying a FW update, so this GPIO should be driven low instead.
BUG=b:193402306
TEST=compile
Change-Id: I976a0b8252b31aacef476d5ee4bcf6b1ef2e79de
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Adds "add" command to elogtool. This command allows adding elog events
manually. It supports event type and, optionally, event data.
If the free buffer space is < 1/4 of the total space, it shrinks the
buffer, making sure that ~1/4 of the free space is available.
BUG=b:172210863
TEST=./elogtool add 0x17 0101
./elogtool add 0x18
Repeated the same tests on buffers that needed to be shrunk.
Change-Id: Ia6fdf4f951565f842d1bff52173811b52f617f66
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add mipi panel support for wormdingler
- Add the following panel for wormdingler:
INX P110ZZD-DF0
BOE TV110C9M-LL0
- Use panel_id to distinguish which mipi panel to use.
- Setup panel orientation
BUG=b:195898400,b:198548221
BRANCH=none
TEST=emerge-strongbad coreboot
Change-Id: I8cd28e024ecbfdcd473bc39efb529eb4aca1b5d0
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
