4 Commits

Author SHA1 Message Date
John Zhao
54a03e43af soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS
This change provides access to IOE through P2SB Sideband interface for
Meteor Lake TCSS functions of pad configuration and Thunderbolt
authentication. There is a policy of locking the P2SB access at the end
of platform initialization. The tbt_authentication is read from IOM
register through IOE P2SB at early silicon initialization phase and its
usage is deferred to usb4 driver.

BUG=b:213574324
TEST=Built coreboot and validated booting to OS successfully on MTLRVP
board. No boot hung was observed.

Signed-off-by: John Zhao <john.zhao@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8dcee90080c6e70dadc011cc1dbef3659fdbc8f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66951
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26 04:13:51 +00:00
Subrata Banik
c6d6f60bc4 Revert "soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS"
This reverts commit eb80b1efa36c99e485b2604e913c2aa316168eea.

Reason for revert: Results into hard hang with serial debug msg inside FSP-S.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8e7cf804828da8939f591eb0770c8daf830c8d94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-18 07:17:35 +00:00
John Zhao
eb80b1efa3 soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS
This change provides access to IOE through P2SB Sideband interface for
Meteor Lake TCSS functions of pad configuration and Thunderbolt
authentication. There is a policy of locking the P2SB access at the end
of platform initialization. The tbt_authentication is read from IOM
register through IOE P2SB at early silicon initialization phase and its
usage is deferred to usb4 driver.

BUG=b:213574324
TEST=Built coreboot and validated booting to OS successfully on MTLRVP
board. No boot hung was observed.

Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-12 17:11:22 +00:00
Ravi Sarawadi
8069b5d3f2 soc/intel/mtl: Do initial Meteor Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API

BUG=b:224325352
TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63363
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-29 05:27:52 +00:00