Configuring GPP_B7 as GPO_HIGH.
Sasuke doesn't have SAR sensor, GPP_B7 is routed to the LTE module
and is kept high so that the LTE module uses the default emission power.
BUG=b:180492044
BRANCH=firmware-dedede-13606.B
TEST="FW_NAME=sasuke emerge-dedede coreboot"
Change-Id: Ib38c649830db2291b3a2a771f5c884acf37dcbeb
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51049
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the temperature sensors defined in baseboard do not exist in
magolor. With the format the DPTF policies are defined in magolor, all
the entries from the baseboard are included and then the overrides
applied. This causes the non-existent DPTF devices to be exported in
the ACPI table and in turn OS reading invalid temperatures. Fix the
format for DPTF passive and critical policies.
BUG=None
BRANCH=dedede
TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Some of the temperature sensors defined in baseboard do not exist in
madoo. With the format the DPTF policies are defined in madoo, all the
entries from the baseboard are included and then the overrides applied.
This causes the non-existent DPTF devices to be exported in the ACPI
table and in turn OS reading invalid temperatures. Fix the format for
DPTF passive and critical policies.
BUG=b:182513022
BRANCH=dedede
TEST=Build and boot to OS in madoo. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Idc5d0b357d61b9346b4d20ec8322b124c9655b4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same
PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in
difference to the X11SSH-F which only has 2 NICs. The two additional
NICs aren't populated on the X11SSH-F. Enable the PCIe root ports
connected to the two additional Intel NICs.
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Drop the 100ms delay in the _PS0 method because kernel already adds this
100ms. This change also drops polling TBT PCIe root ports Link Active
State because this scheme is not applicable for SW CM.
BUG=None
TEST=Built Alderlake coreboot image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 4 and provide the reset GPIO / src clk pin.
BUG=none
TEST=Boot to OS, verify the link is in L2 state during S0ix.
Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.
Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.
Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50898
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the CNVi BT PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.
Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FSP has added the Cnvi BT Core enabling in addition to the existing
CnviMode. This change adds the flag at the soc config side (i.e.
soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host
interface for BT. Therefore, BT core should not use the pci port status to turn
on/off.
TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make
sure BT is turned on.
Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use VPD of "coreboot_uart_io" to select uart io if
OVERRIDE_UART_FOR_CONSOLE is selected.
Tested=On OCP Delta Lake, console messages correctly output to uart
port which is defined in VPD.
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Create the collis variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:182227204
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COLLIS
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ibcf8b59b38d02517cea0a3ee474ff82fc0a2a958
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Override SMBIOS type 2 board feature flags. For Delta Lake, board is
replaceable and is a hosting board.
Tested=Execute "dmidecode -t 2" to check info is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I4469360ec51369dbf8179b3cbac0519ead7f0382
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This patch overrides the get_wifi_sar_cbfs_filename()
to return different sar table according to the sku id.
BUG=b:173465272
TEST=checked bios log and the correct sar table was loaded.
Change-Id: Ia30d760b1a029197d470818c73bfd2c00514652d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update GPP_A10 and GPP_H17 configuration to meet LTE power sequence
specification.
- FCPO (GPP_A10) should not turned off during warm reset.
BUG=b:177177967
BRANCH=dedede
TEST=Verified LTE power signal waveforms during powering on and off
Change-Id: I469f9c94ebd6bf2b68a0edc74f229158d82d0ef8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
I was bugged by spurious "Failed to enable LTR" messages for years.
Looking at the the current algorithm, it is flawed in multiple ways:
* It looks like the author didn't know they implemented a
recursive algorithm (pciexp_enable_ltr()) inside another
recursive algorithm (pciexp_scan_bridge()). Thus, at every
tree level, everything is run again for the whole sub-
tree.
* LTR is enabled no matter if `.set_ltr_max_latencies` is
implemented or not. Leaving the endpoints' LTR settings
at 0: They are told to always report zero tolerance.
In theory, depending on the root-complex implementation,
this may result in higher power consumption than without
LTR messages.
* `.set_ltr_max_latencies` is only considered for the direct
parent of a device. Thus, even with it implemented, an
endpoint below a (non-root) bridge may suffer from the 0
settings as described above.
* Due to the double-recursive nature, LTR is enabled starting
with the endpoints, then moving up the tree, while the PCIe
spec tells us to do it in the exact opposite order.
With the current implementation of pciexp_scan_bridge(), it is
hard to hook anything in that runs for each device from top to
bottom. So the proposed solution still adds some redundancy:
First, for every device that uses pciexp_scan_bus(), we enable
LTR if possible (see below). Then, when returning from the bus-
scanning recursion, we enable LTR for every device and configure
the maximum latencies (if supported). The latter runs again on
all bridges, because it's hard to know if pciexp_scan_bus() was
used for them.
When to enable LTR:
* For all devices that implement `.set_ltr_max_latencies`.
* For all devices below a bridge that has it enabled already.
Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
