Add explicit CBMEM_STAGE_CACHE option. Rename
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.
Platforms with SMM_TSEG=y always need to implement
stage_cache_external_region(). It is allowed to return with a
region of size 0 to effectively disable the cache.
There are no provisions in Kconfig to degrade from
TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.
As a security measure CBMEM_STAGE_CACHE default is changed to
disabled. AGESA platforms without TSEG will experience slower
S3 resume speed unless they explicitly select the option.
Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sometimes the display native orientation does not match the device
default orientation. We add a parameter to be passed to libpayload,
which can then do the rotation.
BUG=b:132049716
TEST=Boot krane, see that FW screen is orientation properly.
Change-Id: I5e1d94b973a3f615b73eebe0ca1202ba03731844
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Caller needs to take into account that bus numbers may
have not been assigned yet. Same issue existed before
with early ramstage and mostly does not cause problems
when used with static devices on bus 0.
Change-Id: I4865b4277dbc858c8c2ffd2052defcaa1a92173c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34614
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ...
- adds the PCH ID for C232 chipset,
- renames "Premium" chipset to "HM170" (because of same IDs),
- reorders the Skylake-H PCH IDs ascending by hex values.
Used documents:
- Intel 332690-005EN
Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
* Move armv7 RAM dection to a common place
* Enable it for all emulated platforms
* Use 32bit probe values and restore memory even on failure
* Use the new logic on the following boards:
** qemu-armv7
** qemu-riscv
Tested on qemu-system-riscv:
Fixes kernel panic due to wrong memory limits reported.
Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
So far the bootsplash is only correctly rendered if the framebuffer is
set up as 1024x768@16.
Different resolutions did not show anything, differnent depth resulted
in the distorted images.
This commit removes this limit by using the actual framebuffer resolutions
and combines the code for x86 and yabel.
For the moment the bootsplash is still limited to VGA-OptionROM
framebuffer init.
It was tested in 1280x1024@32 on the wip razer blade stealth using the
intel vgabios.
Change-Id: I5ab7b8a0f28badaa16e25dbe807158870d06e26a
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34537
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves SPI_FLASH time-outs from spi/spi_flash_internal.h for
SPI SW-sequencing to include/spi-generic.h to provide also for
SPI HW-sequencing.
tested on siemens/bdx1 and checked if all includes of
spi_flash_internal.h on other places provide an include of
spi-generic.h before
Change-Id: I837f1a027b836996bc42389bdf7dbab7f0e9db09
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch lists all supported vesa mode by oprom
using Function 0x4F00 (return vbe controller information).
This information might be useful for user to select correct vesa
mode for oprom.
TEST=Enabling external pcie based graphics card on ICLRVP
Case 1: with unsupported vesa mode 0x118
Now coreboot will show below msg to user to know there is a potential
issue with choosen vesa mode and better users know the failure rather
going to depthcharge and debug further.
Calling Option ROM...
... Option ROM returned.
VBE: Getting information about VESA mode 4118
VBE: Function call invalid with unsupported video mode 0x118!
User to select mode from below list -
Supported Video Mode list for OpRom are:
0x110
0x111
0x113
0x114
0x116
0x117
0x119
0x11a
0x165
0x166
0x121
0x122
0x123
0x124
0x145
0x146
0x175
0x176
0x1d2
0x1d4
Error: In vbe_get_mode_info function
Case 2: with supported vesa mode 0x116
Calling Option ROM...
... Option ROM returned.
VBE: Getting information about VESA mode 4116
VBE: resolution: 1024x768@16
VBE: framebuffer: a0000000
VBE: Setting VESA mode 4116
VGA Option ROM was run
Change-Id: I02cba44374bc50ec3ec2819c97b6f5027c58387f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34284
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms
and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There are only minimal differences between the architecture specific
stdint.h implementations, so let's tidy them up and merge them together
into a single file. In particular,
- Use 'unsigned long' for uintptr_t. This was already the case for x86
and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64
used 'unsigned long long'. This change allows using a single integer
type for uintptr_t across all architectures, and brings it into
consistency with the rest of the code base, which generally uses
'unsigned long' for memory addresses anyway. This change required
fixing several assumptions about integer types in the arm code.
- Use _Bool as the boolean type. This is a specialized boolean type that
was introduced in C99, and is preferrable over hacking booleans
using integers. romcc sadly does not support _Bool, so for that we
stick with the old uint8_t.
- Drop the least and fast integer types. They aren't used
anywhere in the code base and are an unnecessary maintenance burden.
Using the standard fixed width types is essentially always better anyway.
- Drop the UINT64_C() macro. It also isn't used anywhere and doesn't
provide anything that a (uint64_t) cast doesn't.
- Implement the rest of the MIN and MAX numerical limits.
- Use static assertions to check that the integer widths are correct.
Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It is recommended to never reference PCI busses
using a static number. There is exception with
OPROM execution, where we want to translate the
bus number captured from the actual IO operation
into a matching device node in the devicetree.
Change-Id: I733c645ac5581c000b4cd6cdc05829cd039324d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To clear all DRAM on x86_32, add a new method that uses PAE to access
more than 32bit of address space.
Add Documentation as well.
Required for clearing all system memory as part of security API.
Tested on wedge100s:
Takes less than 2 seconds to clear 8GiB of DRAM.
Tested on P8H61M-Pro:
Takes less than 1 second to clear 4GiB of DRAM.
Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function is duplicated in many AMD northbridge files, and all
the definitions have started to diverge somewhat. This moves a single
copy into device utils and deletes the rest. The function definition
from nb/amd/amdfam10 was chosen to be kept, since it contains several
fixes from commit 59d609217b (AMD fam10: Fix add_more_links) that
the others don't have.
For the ease of diffing, the checkpatch lints and other small cleanups
will be done in a follow-up patch.
Change-Id: I5ea73126092449db3f18e19ac0660439313072de
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33237
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sometimes coreboot needs to compile external code (e.g.
vboot_reference) using its own set of system header files. When
these headers don't line up with C Standard Library, it causes
problems.
Create ctype.h header file. Relocate ctype.h functions from
string.h into ctype.h. Update source files which call ctype.h
functions accordingly.
Note that ctype.h still lacks five functions which are not used
in coreboot source:
isalnum, isalpha, iscntrl, isgraph, ispunct
BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I31b5e8af49956ec024a392a73c3c9024b9a9c194
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set
to ENV_RAMSTAGE.
This approach will help to add future optimization (rampayload) in
coreboot flow if required.
Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
This patch adds support to boot FIT image configurations consisting of
a base device tree and one or more overlays. Since extracting the right
compatible string from overlay FDTs is problematic, we'll only support
this for FIT images that have the compatible string pulled out into the
config node.
This patch was adapted from depthcharge's http://crosreview.com/1555293
Change-Id: I0943f9a1869c9e416887c7ff16e33f7d91b74989
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32873
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes some minor refactoring to the way the FIT parser
handles config nodes. A lot of this code was written in the dawn age of
depthcharge when its device tree library wasn't as well-stocked yet, so
some of it can be rewritten nicer with more high-level primitives.
There's no point in storing both the string name and the actual FDT node
of a FIT image node separately, since the latter also contains the
former, so remove that. Also eliminate code for the case of not having
an FDT (which makes no sense), and move some more FDT validity/compat
checking into fit_update_compat() (mostly in anticipation of later
changes).
This patch was adapted from depthcharge's http://crosreview.com/1553456
with a couple of modifications specific to coreboot's custom FIT loading
code.
Change-Id: Ia79e0fd0e1159c4aca64c453b82a0379b133350d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32870
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
