This change will allow the SMI handler to write to the cbmem console
buffer. Normally SMIs can only be debugged using some kind of serial
port (UART). By storing the SMI logs into cbmem we can debug SMIs using
`cbmem -1`. Now that these logs are available to the OS we could also
verify there were no errors in the SMI handler.
Since SMM can write to all of DRAM, we can't trust any pointers
provided by cbmem after the OS has booted. For this reason we store the
cbmem console pointer as part of the SMM runtime parameters. The cbmem
console is implemented as a circular buffer so it will never write
outside of this area.
BUG=b:221231786
TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are
visible when running `cbmem -1`. Perform a suspend/resume cycle and
verify new SMI events are written to the cbmem console log.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash
layout for brya is of 32MB size, and nissa is expected to have 16MB SPI
NOR flash. The current composition of AP firmware exceeds 16MB. To get
an estimate of the unutilized region in the current flash layout for
nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware
size to under 16MB and to remove the RW_UNUSED regions from the final
fmd file.
Below table gives the size reduction from brya fmd to nissa fmd:
+----------------+-------------------+---------------+
| Region | Earlier size (KB) | New size (KB) |
+================+===================+===============+
| SI_ME | 5116 | 3772 |
+----------------+-------------------+---------------+
| RW_SECTION_A/B | 8192 | 4344 |
+----------------+-------------------+---------------+
| VBLOCK_A/B | 64 | 8 |
+----------------+-------------------+---------------+
| ME_RW_A/B* | 3008 | 1434 |
+----------------+-------------------+---------------+
| RW_LEGACY | 2048 | 1024 |
+----------------+-------------------+---------------+
| RW_ELOG | 16 | 4 |
+----------------+-------------------+---------------+
| SHARED_DATA | 8 | 4 |
+----------------+-------------------+---------------+
| VBLOCK_DEV | 8 | 0 |
+----------------+-------------------+---------------+
| RW_SPD_CACHE | 4 | 0 |
+----------------+-------------------+---------------+
| RW_NVRAM | 24 | 8 |
+----------------+-------------------+---------------+
| WP_RO | 8192 | 4096 |
+----------------+-------------------+---------------+
| GBB | 448 | 12 |
+----------------+-------------------+---------------+
*Based on LZMA compression on ME_RW_A/B regions. With LZMA compression,
this region can be 1434K. Without this, ~665K will be more in each of
these regions.
Patch: https://review.coreboot.org/c/coreboot/+/62358/
BUG=b:202783191
BRANCH=None
TEST=Build and boot Nivviks.
Cq-Depend: chrome-internal:4584911
Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on
ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to
ME_RW_A/B regions.
On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B
regions.
FMAP REGION: ME_RW_A
Name Offset Type Size Comp
me_rw 0x0 raw 1275246 LZMA
(1957888 decompressed)
(empty) 0x1375c0 null 193056 none
FMAP REGION: ME_RW_B
Name Offset Type Size Comp
me_rw 0x0 raw 1275246 LZMA
(1957888 decompressed)
(empty) 0x1375c0 null 193056 none
Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
With LinuxBoot Linux relied on the legacy method of fetching the RSDP
pointer to get ACPI. This uses a more modern approach available since
2018 on the Linux kernel, which involves filling in the zero page.
This method takes precedence over any other method of fetching the
RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are
threatening that legacy code will be removed from Linux so it's best
to already adapt to that possibility.
Tested on Qemu:
- With qemu the RSDP is always in the EBDA, so checking if Linux uses
the provided pointer is better done with a forced bad entry
- With a fake bad pointer Linux correctly does not find RDSP
Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ACPI RSDP can only be found in:
- legacy BIOS region
- via UEFI service
On some systems like ARM that legacy BIOS region is not an option, so
to avoid needing UEFI it makes sense to expose the RSDP via a coreboot
table entry.
This also adds the respective unit test.
Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If it is not cleared and the number of strings is fewer than last
iteration, the match[3] will keep the last value, which actually
should be empty.
Add assert to make sure the level is a legal value.
BUG=b:222038278
Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add PCIe support for MediaTek platform.
Reference:
- MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
- linux/drivers/pci/controller/pcie-mediatek-gen3.c
This code is based on MT8195 platform, but it should be common in each
platform with the same PCIe IP in the future.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle
time. Encode tCKMin as per the respective advisories.
BUG=None
TEST=Generate the SPD and ensure that tCKMin is encoded accordingly.
Minimum CAS Latency time is also impacted and is encoded accordingly.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Git uses the .mailmap file to map author and committer names and email
addresses to canonical real names and email addresses.
Before adding this file, coreboot shows 1388 different author names and
email addresses because of typos, people changing email addresses, and
spelling their names differently.
After adding the file, the number of authors is down to 1016.
I tried to determine the best email address for each person by looking
at what they'd used most recently, but I can't promise that I correctly
picked the right address for everyone. Please take a look to make
sure that your email address and name is correct.
To enable .mailmap parsing globally, use:
$ git config --global log.mailmap true
To enable it just for a single log, run:
$ git log --use-mailmap
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1f9b9bccc9322799234475a1cebf9808edd25693
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Denverton is a special version of IFD2 flash layout. It defines
10GbE firmware regions (11/12) and the IE (10) region which
other IFD2 platforms do not have. Denverton does not include the
legacy GbE region (3) or the EC region (8) which other IFD2
platforms do have.
TEST='ifdtool -p dnv coreboot.rom' and verify correct output
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When entering suspend, ACPI support is disabled by setting OSFG to 0x00.
This has been moved to be the final action, so it is after saving the
current EC settings.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5705efab42d2fe0fd5abc6c17eeea46ead27db17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set the log level to BIOS_NOTICE for the case where the mainboard can
not provide a MAC address since this can be a valid case. Showing this
message with log level BIOS_ERR is not appropriate.
In addition, rephrase the message to make clear that if the mainboard
does not provide a MAC address the one stored in the MAC will be used.
Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Currently the BayHub eMMC controller is only going into its reset
state when the RTD3 sequence is initiated. This causes it to
still consume too much power in suspend states. This CL adds the
power enable GPIO into the RTD3 sequence as well, which will turn
off the eMMC controller (a true D3cold state) during the RTD3
sequence.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 100 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.
BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows mainboards using an I2C bus to communicate with the cr50
to reuse the functionality related to firmware version and BOARD_CFG.
BUG=b:202246591
TEST=boot on brya0, see cr50 FW version in logs
Change-Id: Ide1a7299936193da3cd3d15fdfd1a80994d70da0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Mainboards accessing the cr50 over an I2C bus may want to reuse some of
the same firmware version and BOARD_CFG logic, therefore refactor this
logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses
the new tis_vendor_read/write() functions in order to access the cr50
regardless of the bus which is physically used. In order to leave SPI
devices intact, the tis_vendor_* functions are added to the SPI driver.
BUG=b:202246591
TEST=boot to OS on google/dratini, see the same FW version and board_cfg
console prints as before the change.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Windows complains on missing drivers for these ACPI devices. Hide them
from OS as it doesn't influence the hardware operation. Linux can
still probe the drivers correctly.
TEST=Boot Windows 11 and see there are no devices with missing drivers.
Boot Ubuntu 20.04 and check that drivers corresponding to ACPI HIDs are
still probed.
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: I6c30c08ab730749bddef7ea67c7470c1554bd572
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ChromeOS considers the WWAN devices to be untrusted, therefore enable
the new DmaProperty in the WWAN's _DSD to indicate to the OS that these
devices should have IOMMU restrictions applied to them.
BUG=b:215424986
BRANCH=brya
TEST=dump SSDT
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Commit ebf14826
[mb/google/hatch/var/jinlon: Switch to using device pointers]
broke jinlon boards without an electronic privacy screen (EPS) by
disabling the parent device (iGPU) instead of the EPS when determined to
be not present via SKU ID.
Commit c5a3a4a6
[mb/google/hatch (baseboard): add ACPI backlight support]
broke EPS detection by adding a duplicate iGPU device to the devicetree,
resulting in the EPS entry being skipped.
Fix both of these issues by assigning the device alias to the EPS child
device, not the parent (iGPU). Rename the alias for clarity, and combine
the duplicate device definitions for the iGPU.
Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional
in both firmware boot screens and Linux OS.
Change-Id: I0615ce361497abe6872085b0dec83292607e53dd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 017b5c453a
[ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config]
broke tablet mode on google/caroline and cave in mainline Linux kernels
by changing the inclusion of the ChromeEC tablet mode ACPI handler. Fix
this by addding it back (using the updated name guarding the inclusion
of the tmbc ACPI).
Test: build/boot google/cave under Linux 5.16, observe tablet mode
handled correctly.
Change-Id: Ie0ae5b6a61f104b5e973383344d289cc2e2a7b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
