Commit Graph

8 Commits

Author SHA1 Message Date
Stefan Reinauer
5ff2502151 intel/skylake: Fix flash_controller.c compilation
Since this code is not currently being built by coreboot, it
failed compilation.

Change-Id: Ib8a0e1ebc76b7dca3dd785b09398b73abad46366
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12466
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 20:22:34 +01:00
Patrick Georgi
a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Aaron Durbin
11f356c390 skylake: refactor flash_controller code
There's no need to add any typedefs nor guard code with
ENV_ROMSTAGE. The linker will garbage collect unused functions.
Additionally there were a few errors in the code including
the operation mask wasn't wide enough to clear out old operations
as well as component size decoding was incorrect.

The big difference in the code flow is that the operation
setup is now in one place. The stopwatch API is also used in
order to not open code time calculations.

BUG=chrome-os-partner:42115
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted. Suspended and resumed. event log is populated
     for all.

Change-Id: I0ddd42f0744cf8f88da832d7d715663238209a71
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9893fe309104c05edfb158afda6bb029801c0489
Original-Change-Id: I6468f5b9b4a73885b69ebd916861dd2e8e3746b6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295980
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11543
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:30:11 +00:00
Aaron Durbin
ce03aaf08c skylake: move flash_controller.h to the proper place
I missed this in code review. This should be under the soc
directory.

BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built glados.

Change-Id: Ia018c20f97f267b8f7592b2459d10eafe5ec7159
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c081ed6de46605b7d0a72962ac2a041c470b12c
Original-Change-Id: Ic3938fe5d71bd24a395304cfabe40eff48bc4a40
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295239
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11542
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:29:53 +00:00
Aaron Durbin
394d6993b9 skylake: fix eventlog on resume path
The spi_init() routine needs to be called in all boot paths to allow
writes to the SPI part. The reason is that the write enable is done
in spi_init(). Moreover, this is also required for a writing a firmware
update after a resume.

BUG=chrome-os-partner:42115
BRANCH=None
TEST=Built and booted glados. Suspended and resumed. Eventlogs show
     up in resume path.

Change-Id: I187baa940bb45ef90ab82e67c02f13d8855d364e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8813ab227395cfcba46ad4109730a1eb5897e538
Original-Change-Id: Ida726fc29e6d49cd9af02c4e57125e09f2599c36
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295238
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11541
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:22:36 +00:00
Stefan Reinauer
4460703f59 Drop "See file CREDITS..." comment
coreboot has no CREDITS file.

Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-07 15:54:50 +00:00
Subrata
d92f6127e1 intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access.
Created generic library to implement SPI read, write, erase and
read status functionality for both ROMSTAGE and RAMSTAGE access.

BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and verify SPI read, write,
erase success from ELOG.

Change-Id: Idf4ffdb550e2a3b87059554e8825a1182b448a8a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 74907352931db78802298fe7280a39913a37f0c2
Original-Change-Id: Ib08da1b8825e2e88641acbac3863b926ec48afd9
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294444
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Commit-Queue: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: http://review.coreboot.org/11422
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29 07:23:57 +00:00
Lee Leahy
1d14b3e926 soc/intel: Add Skylake SOC support
Add the files to support the Skylake SOC.
Matches chromium tree at 927026db

BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform

Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16 17:24:48 +02:00