This header implements structures to describe the properties defined in
the SoundWire Discovery and Configuration Specification Version 1.0.
By itself this just provides the property definitions, it is then used
by the code that generates ACPI device properties and by the controller
and codec drivers.
A new header for MIPI vendor/device IDs is also added, with the MIPI
Alliance board members added by default. This will be used in the same
way as pci_ids.h to track devices added to coreboot.
BUG=b:146482091
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ie9901d26d1efe68edad7c049c98a976c4e4f06f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The common PnP serial port DSDT code is intentionally included twice for
two serial ports with different LDNs. Undefine LDN and the PM register
name before redefining for second serial port so iasl doesn't complain.
Change-Id: I031905479c66698fb01da028e3f37d923396d2d9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41095
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current implementation uses strcmp() without splitting the list
and therefore returns false even when the string pointed to by
'name' is a part of 'whitelist'. The patch fixes this problem.
Also, update help text of CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA to
space delimited list to align it with the other lists we use.
Change-Id: Ifd285162ea6e562a5bb18325a1b767ac2e4276f3
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The IOSAV register descriptions are plagued with errors and nonsense.
Using `git blame` to find the culprit... Zoinks! Turns out it was me!
Rewrite the comment so that the difference between a sub-sequence and a
command is clear. Also, expand the descriptions that could be ambiguous
and fix some insane blunders. CKE and ODT fields are per DIMM and rank!
As per review comments, also invert the order of bitfield value ranges.
Change-Id: Ie384304c565f962fe58baa231c15109eb3d284aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch adds a basic test for the common region and region_device
APIs, sanity checking the basic functions and things like
overflow-handling. There is certainly more that could be added here, but
it's a start.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4932402f54768557e5b22b16e66220bd90ddebfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41046
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jan Dabros
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<cmocka.h> requires a few standard headers to be explicitly included
before itself or it will throw compilation errors. Having to always
include these headers in the right order in every test is cumbersome.
Instead, this patch encapsulates the problem in a new <tests/test.h>
header that all tests should include (instead of <cmocka.h> directly).
Also fix --gc-sections in the test framework which needs to be passed
for linking, not for compiling.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4284d74c8673708e21a5266eb42f7b9ae19a1b12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Fix unterminated array.
When looking for a type not specified in filetypes (cbfs.h:204), the
loop in lookup_name_by_type (cbfs_image.c:60) will run into a buffer
over-read.
Found-by: AFL++ 2.64d rev 1317433
Signed-off-by: Philipp Bartsch <phil@grmr.de>
Change-Id: Ib82bb92e82b09fa1e26b9ca34529ec7b98e8f7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41421
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No code that was or will be upstreamed uses functionality from soc_util
in romstage, so only compile and link it for ramstage.
This also allows to fix the SoC type detection in a follow-up patch
using information that FPS-M will be providing in a HOB.
BUG=b:153779573
Change-Id: If96e53608eadd562f6de5a0c370b89e84e43d049
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The struct (formerly assigned to default_pci_ops_bus.ops_pci) only
contained a NULL (well, 0) pointer for the set_subsystem callback, but
usage of that callback is guarded with NULL checks when it is used,
therefore it can be removed.
TEST=still compiles
Change-Id: I3943c8ae73b95e744a317264d7ceb8929cb28341
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41432
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update processor power limit configuration parameters based on
common code base support for Intel Broadwell SoC based platforms.
BRANCH=None
BUG=None
TEST=Build for broadwell based platform
Change-Id: I97e38a533e74a122b6809e20a10f6e425827ab9c
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Don't directly include <soc/gpio.h>. All code using GPIO features
should always and only include <gpio.h>, which should indirectly
include the SoC-specific <soc/gpio.h>.
Change-Id: I78f1e250570f1b395c61115d4a872b24b3d58f69
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Don't directly include <soc/gpio.h>. All code using GPIO features
should always and only include <gpio.h>, which should indirectly
include the SoC-specific <soc/gpio.h>.
Change-Id: Id2663398b9f069ab1f60d63016ea7aa080f66d20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Add function to display ME Host Firmware Status registers. Make use of
print_me_fw_version() from CSE lib to print ME firmware version information.
Add manufacturing mode field in HFSTS1 register for JSL in place of,
spi_protection_mode in TGL.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp. In coreboot logs, ME info can be seen.
ME: Version: 13.5.0.7049
ME: HFSTS1 : 0x90006255
ME: HFSTS2 : 0x82100136
ME: HFSTS3 : 0x00000020
ME: HFSTS4 : 0x00004800
ME: HFSTS5 : 0x00000000
ME: HFSTS6 : 0x00400006
ME: Manufacturing Mode : YES
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : YES
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: D0i3 Support : YES
ME: Low Power State Enabled : NO
ME: CPU Replaced : YES
ME: CPU Replacement Valid : YES
ME: Current Working State : 5
ME: Current Operation State : 1
ME: Current Operation Mode : 0
ME: Error Code : 6
ME: CPU Debug Disabled : YES
ME: TXT Support : NO
Change-Id: Ic6b1c9410db8f06ac24fd997772b2ede04264bee
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Deltaur uses HDA codec so we need to set iDisplay Audio Codec
disconnection and enable HdaAudioLink, otherwise the HDA codec won't
respond to commands to execute HDA verbs.
BUG=b:156447983
TEST=No timeout error when run "devbeep" in CLI.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I15d2895866abcf68963c9732ed5d05f32096fc92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41397
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The index of DRAM_STRAPS indicates to a specific DRAM characteristic
instead of a DRAM part number therefore update the existing DRAM SPD
binary to the naming by DRAM characteristic.
BUG=b:152019429
BRANCH=None
TEST=build the image and verify that coreboot log shows the correct SPD
info
Change-Id: I8ffcf156f37a465209740c5e2a34effb5f1f5d5c
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reading the SPD using the SMBUS routines takes a long time because each
byte or word is access seperately.
Allow using the i2c read eeprom routines to read the SPD. By doing this
the start address is only sent once per page.
The time required to read a DDR4 SPD is reduced from 200 msec to 50
msec.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I44e18b8ba72e1b2321f83402a6a055e2be6f940c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Update monolith root port settings to match those of the original BIOS.
MaxPayload is set to 256 bytes, ASPM is disabled and LTR and Advanced
Error reporting are enabled.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Idf6e706d45cf1ea1aee4a75a6d0eb130b21db927
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
If panel has too small hfp or hbp, hfp_byte or hbp_byte may become
very small value or negative value. When very small value or
negative value is used, the panel will be scrolling or distorted.
This patch adjusts their values so that they are greater than
the minimum value and keep total of them unchanged.
DSI transfer HBP or HFP, There are some extra packet. ex. packet
header(4byte) and eof(2byte) and (next)hs packet header(4 byte).
the hfp_byte = HFP * BPP - packet header(4byte) and eof(2byte)
and (next)hs packet header(4 byte). So the min hfp_byte is 2 when
HFP = 4.
This is equivalent to the Linux kernel DSI change in:
https://chromium-review.googlesource.com/c/chromiumos/third_party/
kernel/+/2186872
BUG=b:144824303
BRANCH=kukui
TEST=boot damu board with panel CMN N120ACA-EA1 (12" panel and its
hbp only 6), the panel can display without scrolling or
distortions.
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
Change-Id: I608c01d41ae93c8d5094647bbf3e0ae4a23d814c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41163
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default ROMSTAGE_ADDR and VERSTAGE_ADDR are set to 0x2000000. This
causes problems in a non-xip environment because when verstage loads
romstage, it overrides it's memory. So pick a different offset for
verstage.
BUG=b:147042464
TEST=Boot verstage on trembyle and see OS boot.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2464db6f3769bd23d250588b341d1c9e44f10d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPU to PCH method refers to PCH ACPI operation region which was wrongly
defined as SystemIO. This causes ACPI AE_LIMIT error from PM _DSW
method. Change the operation region from SystemIO to SystemMemory to
resolve this execution failure.
BUG=b:140290596
TEST=Built and booted to kernel. _DSW method executes successfully without
ACPI AE_LIMIT error.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3965c3d891f7d3cf4a448edc0c3f7e7749a905a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
