ITE8258_CMD_PORT is used in com_init.c only.
Replace ITE8258_CMD_PORT by fixed value in the c file.
ITE8258_DATA_PORT is removed as this isn't used.
BUG=N/A
TEST=build
Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Location in hudson_lpc_port80() was called conditionally.
Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX()
due the change from IO to MMIO using pm_read/write.
Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Disabling SSL verification is far from optimal, but depending on the
circumstances may be the most practical way, so describe how to do
that instead of leaving users confused.
It's also not _that_ bad because git's hashing scheme should uncover
most attempts to tamper with code, either when checking signed tags
or when people push (and see lots of modified commits).
State the command in a way that isn't conductive to careless
copy & paste.
Change-Id: Idbd52ba5d6e8b0f0e891fca16e4159ccef10771a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These boards currently have no build-testing, so they degrade
fast. Apply some of the build-tested changes we know to be
good from pcengines/apu2 to get them a bit closer to using
POSTCAR_STAGE=y.
Change-Id: Ibc9a15ed5e91c6dd857f2dd02e37d0979dd6ae90
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The bayou payload is not attached to the build system in any way, and
has not been for quite a while. Since selecting it in Kconfig does
nothing, remove this payload now that coreboot 4.10 has been released.
Change-Id: Icfb18b88e460a4e4b538b7efe907d4eef6c40638
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It is an ATX board similar to existing ga-b75* boards. The major
difference is the configuration of pci-e ports on PCH, and on-board
pci-e NIC. (see below)
Tested:
- CPU i5 3570T
- Slotted DIMM 8GiB*4 from Kingston
- usb2 and usb3
- pci and pci-e ports
- sata
- Sound
- S3
- AR8161 NIC connected to 1c.2 with mac address burnt in efuse
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- tpm 1.2 on lpc (similar to ga-b75m-d3h)
- Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from
SeaBIOS.
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is adding a dependency check for the FSP_USE_REPO
config option which so far was not able to deal with IceLake
systems.
Change-Id: I29faa8d3acff5680b611951fc193d33f514dc0d3
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37561
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some return codes were missed when implementing this initially; the vboot
logic can require the system to command the EC to reboot to its RO, switch
RW slots or it can require a poweroff of the SoC. This patch appropriately
handles these return codes.
BUG=b:145768046
BRANCH=firmware-hatch-12672.B
TEST=ODM verified this patch fixes the issues seen.
Change-Id: I2748cf626d49c255cb0274cb336b072dcdf8cded
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change the hex values in the VR configuration tables of the Intel Kaby
Lake RVP boards to the same style that is used in the other mainboards.
Also, correct some numbers in the comment tables that did not match the register values.
The values in the tables haven't changed.
BUG=N/A
TEST=build
Change-Id: I77af544d7d88143e19abedb12a13627779c705c6
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37550
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.
This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The board is booting Linux and has been briefly tested.
SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.
BUG=N/A
TEST=tested on Facebook Monolith
Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
On embedded boards the cpu mounted on the board is known. So it is not
required to include microcode for all possible Sky Lake and Kaby Lake
cpus. This patch provides the possibility to only support the versions
required.
By default all microcode updates will be included and the versions not
required can be removed using Kconfig.
BUG=N/A
TEST=build
Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The code in cpu/x86/lapic/apic_timer.c for timer_monotonic_get()
is not SMP safe as LAPIC timers do not run as synchronised as TSCs.
The times reported for console for boot_states does not accumulate
from APs now. Also remove console time tracking from ENV_SMM.
Change-Id: I1ea2c1e7172f8ab3692b42dee3f669c5942d864a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37398
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
