9a016236d4
soc/intel/skylake/vr_config: Add loadline defaults
...
In addition to zero IccMax specified by mainboard with socketed CPU, allow
a zero LoadLine default.
The SoC code will fill in the default AC/DC LoadLine values are per
datasheets:
* "7th Generation Intel® Processor Families for H Platforms, Vol 1"
Document Number: 335190-003
* "7th Generation Intel® Processor Families for S Platforms and
Intel ®Core™ X-Series Processor Family, Vol 1"
Document Number: 335195-003
The AC/DC LoadLine is CPU and board specific.
TODO: Find out how to get the LoadLine from vendor firmware and find out
how to map those to different CPU LoadLines.
Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34938
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-20 11:14:47 +00:00
69e826dab2
soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S
...
Datasheets used:
* "7th Generation Intel® Processor Families for H Platforms, Vol 1"
Document Number: 335190-003
* "7th Generation Intel® Processor Families for S Platforms and
Intel ®Core™ X-Series Processor Family, Vol 1"
Document Number: 335195-003
This allows mainboards to specify a zero IccMax, which all mainboards with
socketed CPU should do.
Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34937
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-20 09:52:59 +00:00
50aebaf8a0
soc/intel/skylake/vr_config: Get rid of static lookup table
...
Use a switch case to find the correct VR config.
The following commit will add more entries for which a lookup table
isn't the best solution.
Change-Id: Ib11c3d6e1eb339a0c7358c312a32731d835e7c73
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com >
2019-08-20 09:40:45 +00:00
9ef977f595
soc/intel/skylake/vr_config: Get rid of defines
...
Get rid of defines and hardcode values directly.
Just a cosmetic cleanup to make it more readable.
Change-Id: I3eec44b38af356c3d87235740c65e2c2f6fc5876
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
2019-08-20 09:40:18 +00:00
e405c27294
lenovo/pmh7: Remove use of __PRE_RAM__ and __SMM__
...
Change-Id: Ib74c5c8cb9197fa06b2972cb96337fedd7f85b5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2019-08-20 08:41:33 +00:00
85cd7c245c
device/oprom: Drop unnecessary AMD headers
...
Change-Id: I548dfa053f195b1ea87568240bf0041bb193d825
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2019-08-20 08:39:27 +00:00
b843ee6efc
mb/google/kohaku: Use level trigger for touchscreen interrupt
...
Level trigger is recommended setting for touchscreen interrupt of
kohaku, so we would change it as the recommedation.
BUG=b:139179200
BRANCH=none
TEST=Verified touchscreen works on kohaku
Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-08-20 01:48:46 +00:00
dad1cef0c0
AGESA: Define extra CFLAGS just once
...
Change-Id: I91d5a0fa0b5e4575d03eb083fade43f6dbb94c77
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2019-08-20 01:32:14 +00:00
cd2aa47a34
devicetree: Remove duplicate chip_ops declarations
...
These are only referenced inside auto-generated static.c
files, and util/sconfig also generates the declarations
automatically from source file pathnames.
Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-20 01:31:44 +00:00
216f717d31
google/stout: Use MAYBE_STATIC
...
Change-Id: I11027acb11a4656536384134d0caebd14b63770c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2019-08-20 01:30:53 +00:00
8d75f6c247
google/butterfly: Replace use of __PRE_RAM__
...
Change-Id: Iae944b589d587b30826e935feae029aa8d07d5d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2019-08-20 01:16:17 +00:00
a4e8fb2afd
arch/non-x86: Remove use of __PRE_RAM__
...
Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2019-08-20 01:12:28 +00:00
5c82c444fb
commonlib/region: Fix up overflow check in region_is_subregion()
...
region_is_subregion() checks whether the size of the inner region is
larger than the size of the outer region... which isn't really necessary
because we're already checking the starts and ends of both regions.
Maybe this was added to ensure the inner region doesn't overflow? But
it's not guaranteed to catch that in all cases. Replace it with a proper
overflow check.
Change-Id: I9e442053584a479a323c1fa1c0591934ff83eb10
Signed-off-by: Julius Werner <jwerner@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-08-19 21:12:31 +00:00
0889e9392c
intel/fsp2_0: Add TS_BEFORE_RAMINIT and TS_AFTER_RAMINIT
...
Change-Id: I99dbef5d52e4fc6cde22876216052cbe998822cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-08-19 19:48:34 +00:00
a7cac0a681
emulation/qemu-x86: Fix romstage stack alignment
...
Also tidy up some register usage.
Change-Id: I5b4b4a29c854f4ca165cede4e9b6755a6c577e76
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34975
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-19 19:48:07 +00:00
2dba2949fa
google/rambi: Replace __PRE_RAM__ with ENV_ROMSTAGE
...
Change-Id: I9d86f8475221b52ccdb45cdeaf538e85ab7a17c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-08-19 19:47:41 +00:00
063b162008
util/superiotool: add IT8987 detection and register support
...
Signed-off-by: Matt Parnell <mparnell@gmail.com >
Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2019-08-19 10:36:17 +00:00
b93f86601c
ec/google/chromeec: Use MAYBE_STATIC
...
Change-Id: I4c6238b0e5f41fcc667baf6b486c7fff4c90a7cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34944
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-19 00:04:55 +00:00
9c5a9bba8e
mainboard/google: Remove use of __PRE_RAM__
...
Change-Id: I2ebeb393e4a5a4bfac8a37a877d067aca484ca2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-08-19 00:03:37 +00:00
157b189f6b
cpu/intel: Enter romstage without BIST
...
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-08-18 19:03:22 +00:00
146c098233
mainboards: Remove floating __PRE_RAM__ comments
...
Change-Id: I110e54175a81b6a651213e0f18ddc1e3e71160cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-08-18 09:54:08 +00:00
184a1176f3
amdfam10-15: Rename DCACHE_BSP_STACK_SIZE
...
The original name DCACHE_BSP_STACK_SIZE will be exclusively
used to define the fixed size of BSP stack when it is located
near the beginning of CAR region. This implementation has the
stack located at the very end of CAR region.
Remove other fam10-15 exclusive configs from global space.
Change-Id: I8b92891be2ed62944a9eddde39ed20a12f4875c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-08-18 08:09:21 +00:00
126d4198a9
mediatek/mt8183: Add SAMSUNG 4GB LPDDR4X discrete DDR support
...
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test passes on Kukui.
Change-Id: I27164f0909edb9d9398835e292fb845f0e342391
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34532
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Martin Roth <martinroth@google.com >
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-16 19:52:44 +00:00
f4aa501eca
soc/intel/cannonlake: Add 4E/4F to early io init
...
This is needed for the AST2500 to work, because it uses 4E/4F.
Change-Id: Ie47474e9bf1edfe98555a148469c41283e9a4ea6
Signed-off-by: Christian Walter <christian.walter@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2019-08-16 10:42:27 +00:00
ccac15a4dd
soc/intel/cannonlake: Add more PCI Ids for Coffeelake
...
Change-Id: I92e2adb32d19ff49bdef353e1f191c4960ce0d18
Signed-off-by: Christian Walter <christian.walter@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2019-08-16 10:42:05 +00:00
4055cd8b03
soc/intel/common/dptf: Add support for mode-aware DPTF
...
This change ports some previous work for Skylake:
cb58683ef5philipchen@google.com >
Change-Id: I5e7b97d23b8567c96a7d60f7a434e98dd9c69544
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34785
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-16 04:27:55 +00:00
aa3c0a5fad
mb/google/hatch: Create Akemi variant
...
This is based on the hatch variant
BUG=b:138879565
TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp
chromeos-bootimage look for image-akemi.*.bin generated under the
/build/hatch/firmware/
Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-08-16 04:27:40 +00:00
8699724a07
amd/picasso: Unify SMM relocation
...
Change-Id: I62104894b5a956523f509d88d49e45a0bd1c587d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34749
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-16 00:37:31 +00:00
0d4d09cad1
amd/stoneyridge: Unify SMM relocation
...
Change-Id: I02ad07e049cb74ccb52ba3d41eb16c58a2cfb38b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34748
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-16 00:37:00 +00:00
1dbf31014f
amd/stoneyridge: Rename ramtop.c to memmap.c
...
Use a name consistent with the more recent soc/intel.
Change-Id: I4d67a7c3107758c81a67e1668875767beccfcdb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2019-08-16 00:36:37 +00:00
047a9e4ddc
amd/picasso: Rename ramtop.c to memmap.c
...
Use a name consistent with the more recent soc/intel.
Change-Id: I491e609bed00dc79c628b321c74ad7f4cc31b5fe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2019-08-16 00:36:26 +00:00
66cabe7ba2
soc/amd/common: Refactor S3 helpers
...
Make the prototypes match what drivers/amd/agesa would
rather see, in preparation to use the same code with
open-source AGESA.
Change-Id: I1506ee2f7ecf3cb6ec4cce37a030c05f78ec6d59
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2019-08-16 00:35:49 +00:00
434a975b97
mb/google/hatch/var/kindred: Configure GPIOs for eMMC SKUs
...
Configure GPIOs for eMMC SKUs
BUG=b:132918661
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22
Change-Id: I9f678a40555dbc841487811cc1f680b211a51a89
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2019-08-15 20:08:40 +00:00
aa9aff7b81
mb/google/hatch/var/kindred: Disable SATA controller for eMMC SKUs
...
Disable SATA controller and SATA port 1 for eMMC SKUs
BUG=b:132918661
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22
Change-Id: I6d95ff94b079a564f74c19739370101899843f00
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34789
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 20:08:20 +00:00
460a1758aa
mb/google/hatch/var/kindred: Configure GPIOs for SSD SKUs
...
Configure GPIOs for SSD SKUs
BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24
Change-Id: Ief48a2fd2fa078aa5d89aec01f99af75510334b2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34851
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 20:07:47 +00:00
8444e3c47a
mb/google/hatch/var/kindred: Disable eMMC for new SKU ID 23 and 24
...
1. Disable eMMC controller for new SKU ID 23 and 24
2. Disable HS400 mode
BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24
Change-Id: I0d893f0f7339e7b1a1e6b56d1598c0a361c8d604
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2019-08-15 20:07:36 +00:00
2c430c8c5b
intel/smm: Define struct ied_header just once
...
Change-Id: I6fc083aa30d05c11c1b6db7b3facacf5ae857c92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-08-15 06:58:45 +00:00
faf20d30a6
soc/intel: Rename some SMM support functions
...
Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.
Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 06:55:59 +00:00
f091f4daf7
intel/smm/gen1: Rename header file
...
Change-Id: I258fccc5e1db0bedb641c8af8cb9727954d4d7c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-08-15 06:53:52 +00:00
5ec97cea67
soc/*: mp_run_on_all_cpus: Remove configurable timeout
...
Some timeouts given were too small when serial console is enabled due to
its spinlock making code runtime worse with every AP present.
In addition we usually don't know how long specific code runs and how
long ago it was sent to the APs.
Remove the timeout argument from mp_run_on_all_cpus and instead wait up
to 1 second, to prevent possible crashing of secondary APs still
processing the old job.
Tested on Supermicro X11SSH-TF.
Change-Id: I456be647b159f7a2ea7d94986a24424e56dcc8c4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
2019-08-15 06:45:34 +00:00
1bc6bf1152
drivers/ipmi: make IPMI KCS status and command register spacing configurable
...
The default is 1 (byte) spacing.
Tested on Mono Lake with 4 (32-bit) spacing
Change-Id: I47412c32e6db8f58b4fde8150adcbce349ca18a7
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2019-08-15 06:45:08 +00:00
621142aa60
intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR code
...
There was no code present to call wrmsr with the data we
prepared in the structs. The MSRS are already set up by FSP,
just reference with the more recent names of PRMRR and UNCORE_PRMRR.
Change-Id: Ib49e7af52e1170a1304975ff0ae63f99e106dffe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-08-15 05:57:43 +00:00
07b7d8c630
soc/intel: Drop spurious includes
...
Change-Id: I2fff107e38abdd34f2d80d4d258be4c429d371e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-08-15 05:57:07 +00:00
7cdb047ce7
cpu/x86/smm: Promote smm_memory_map()
...
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 05:46:59 +00:00
544878b563
arch/x86: Add postcar_frame_common_mtrrs()
...
As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.
Add possibility for the platform to skip these if
required.
Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 05:32:44 +00:00
5bc641afeb
cpu/intel: Refactor platform_enter_postcar()
...
There are benefits in placing the postcar_frame structure
in .bss and returning control to romstage_main().
Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2019-08-15 05:31:29 +00:00
b3267e002e
cpu/intel: Replace bsp_init_and_start_aps()
...
Change-Id: I7176efdd1000789a093a1b4e243b4b150e6bb06f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34864
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 04:59:12 +00:00
826f35421e
intel/denverton_ns: Drop unused save_gpio_route
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Change-Id: I58131d77ba23024cd23e38584f8062d330d2564f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: David Guckian
2019-08-15 04:42:21 +00:00
89d7fd8100
mainboard/google: Fix indirect includes
...
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 04:41:35 +00:00
a347630641
intel/smm/gen1: Split alternative SMRR register function
...
The non-alternative one will have inlined version available
with the new header.
Change-Id: I208ac84fdf5d8041a1901cc2331769cd3a8d6bea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-08-15 04:40:32 +00:00
