The code currently checks that 4 <= dev_index <= 10, which after
subtraction by 4 can index into an array of length at most 7. This is
fine for the largest cpl array (which does have length 7), but is
too large for some of the others, which are smaller. This adds bounds
checks for each array access to ensure they are all within bounds.
Change-Id: I1610d35ca6cbb6cfb42c251e75b0e8b22b64252b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229676
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The speed argument should be one of the six values from the mem_clock
enum, so something is very wrong if this is not the case. Better to
die now than return 0, which will cause a division-by-zero error
later on where this function is called. The first two speeds are also
unsupported and have the same problem with returning 0, so die on those
as well.
Change-Id: Ib628c0eed3d6571bdde1df27ae213ca0691ec256
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1391088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33409
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the decoded SPD DRAM frequency is slower than the controller minimum,
then there will be an unsigned integer underflow in the following loop,
which will lead to a very large out of bounds array access. Ensure this
does not happen.
Change-Id: Ic8ed1293adfe0866781bd638323977abd110777e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Judging from the state machine on page 281 of the Rockchip RK3288
Technical Reference Manual (Rev 1.0 - Jun 2015), the fall through
from the INIT_MEM -> CONF states is intentional, since that is the
only way to get to the ACCESS state. Add a comment to explain this.
Change-Id: I1d0cfea07211c54d6a906f5a7481c2c760f8ef0d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1291959
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms
and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently, bluetooth FW is not loaded after a reboot. In order to do
this, we have to disable the bluetooth disable gpio (GPP_C14) in
bootblock and re-enable it in ramstage.
BUG=b:137307516
BRANCH=None
TEST=boot up Hatch device and make sure (in dmesg) that proper
bluetooth FW in loaded
Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:137033609
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There are two hard things in computer science: cache invalidation,
naming things, and off-by-one errors. -- Anonymous
var_num records the number of initialized entries in the reg_var array.
However, this means the index of the last initialized element is one
less than the value of var_num, so we need to take that into account
when indexing into the array. This has already been fixed in several
other places (eg. sb/amd/pi/hudson/lpc.c), so let's also do so here.
Change-Id: Ibefabaca42866a3f2b22eff979c73badf86ac317
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
512 bytes is much too big for this buffer, which only needs to hold a
path that will have a length of at most 20. The large buffer size also
triggers a -Wformat-truncation warning with GCC since it is later
printed into the smaller temp_string array, so shrink it down to
something reasonable.
Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The FSP_CAR option has additional configuration options whose default
values result in boot failures. Since default values should always boot,
default to the open-source CAR NEM Enhanced implementation instead. This
also allows us to get rid of an unnecessary vendor-specific special case.
Change-Id: I30b1808f91701c07dce6f1de08c213150e8a675a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34287
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For AMD's Family17h processors, verstage needs to be run in the PSP,
before memory is initialized. This adds that binary into the PSP
directory.
See the Family17h documentation in the coreboot documentation directory
for more information.
BUG=b:137338769
TEST=Build, add test binary to mandolin board, boot
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
- Correct command line argument for microcode patches from -u to -O
- Add #if PSP_COMBO around new_combo_dir() as it's only called when
that's enabled.
- Remove unused variable in integrate_bios_firmwares()
- Correct enum type from amd_fw_type to amd_bios_type in
register_fw_addr()
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
SOR_LINK_SPEED_G5_4 is unsupported, but it is not invalid, so it
suffices to return here instead of printing the next warning message.
Change-Id: Ifca3c52635e9a39af42e6616821d1099c43c237c
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1293137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
last_unitid is immediately overwritten in the do loop, so this assignment
is not needed. This a relic from old code that commit 13f1c2af8b made
obsolete, but was never removed.
Change-Id: I2eecddd025f7a64b0a70fc07a61ebb43aba757d6
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The JUnit output from the libpayload builds was getting deleted by the
coreinfo build. Move the libpayload to later in the coreboot-gerrit
job.
Also add messages to stdout indicating the various libpayload configs
that are built and a message indicating when all libpayload builds are
complete.
BUG=b:137380189
TEST=Upload test commit that includes a libpayload compile error and
verify buildbot fails.
Change-Id: I43b55f402216582dcf81be34171437be345572ab
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add generic WiFi driver to support common device operations across
multiple types of WiFi controller.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables
and wakeup GPE information. Ensure that the SSDT table is same after the
change.
Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
