EC software sync had been disabled because BIOS was not bundling a
useful EC image. This is no longer required. This CL removes that
change so EC software sync is enabled by default.
BUG=b:124208414
BRANCH=None
TEST=Tested with a system that have a different RW image and verified
that this image was overwritten to the one bundled in the BIOS and
that the EC was running its RW image.
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5
Reviewed-on: https://review.coreboot.org/c/31537
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For CFL and WHL, Microcode is being loaded from FIT. Both
supports the PRMRR/SGX feature. If This is supported the FIT
microcode load will set the msr (0x08b) with the Patch id one
less than the id in the microcode binary. This results in
Microcode getting reloaded again in bootblock and ramstage.
Avoid the microcode reload by checking for PRMRR support.
CFL and WHL CPU die are based on KBL CPU so we need to have
this check, where CNL CPU die is not based on KBL CPU so
skip this check for CNL.
BUG=b:124126405
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955
Reviewed-on: https://review.coreboot.org/c/31492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
The default mapping was probably copy-pasted from a random
board and disabled some interrupts (by implicitly clearing
some register bits).
We provide a new default mapping with some reasoning, that
tries to be most compatible (i.e. avoids to use PIRQ E-H
that are not shareable on some boards).
The following functions had their interrupt pin disabled
before:
o SATA 2 (explicitly, no board seems to enable the device)
o PCIe Root Port #4, #6-#8 (probably by accident)
PIRQs used before this change: A-D, F and H. After this
change: A-D.
Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31498
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"
Change-Id: I139c5c7b33671e7ed0c04c06fb290e001e57a687
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"
Change-Id: I7da9dcd68f5eec6383de7370bc8ab35f96a90c06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We used .aml as the file extension for preprocessed ASL code. That
file gets overwritten with the compilation results, fix that.
Change-Id: I11a03dfbcebb0fd762da7b27862a7bdb9a581b92
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Variants of Hatch need to accommodate single channel DDR. Also,
removing const modifier as we'll need to set these fields
incrementally now. For the single channel configuration, we set
MemorySpdPtr10 to 0. For the dual channel configuration, we set
MemorySpdPtr10 to MemorySpdPtr00.
BUG=b:123062346, b:122959294
BRANCH=None
TEST=Boot into current boards and ensure that we have 2 channels as expected
Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31262
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch feeds PsysPmax setting to FSP through UPD and adds a
psys_pmax member in chip information so that we can set PsysPmax
through DT. The PsysPmax needs to be set correctly mapping to maximum
system power. Otherwise, system performance would be limited due to
the default PsysPmax setting in FSP is only 21W.
BUG=None
BRANCH=None
TEST=Set psys_pmax to an example value eg 101 in DT && put debug code
in FSP to print the PsysPmax value before sending to Pcode, ensure
the setting is correctly programmed.
Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/31505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the _DSM method 5 and 6 for entering and exiting S0ix.
The _DSM method gets injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db
Reviewed-on: https://review.coreboot.org/c/31101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The requirements read a bit as if we only encourage coreboot experts to
try to take on these projects. These requirements should be understood
as "this is what you'll need to learn", hopefully guiding interested
people in picking a project that suits their interests.
Change-Id: I43b6e2e0df5f00e1ded8d14cee8c771e3f595ce7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31480
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Static scan-build indicates a possible invalid return from function
spi_flash_cmd_erase(). The root cause is because the scan believes it's
possible for offset to be above the end address in the first pass, thus
not setting a value for variable ret. Assign initial value of -1 to
variable ret to make checker happy.
BUG=b:112253891
TEST=build grunt
Change-Id: If548728ff90b755c69143eabff6aeff01e8fd483
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
"mosys memory spd print all" returns incorrect memory ranks info.
This patch and 2 upcomming ones (one in FSP) will address the issue.
BUG=b:122329046
TEST=Boot to OS on Bobba variant of Octopus
BRANCH=octopus
Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Reviewed-on: https://review.coreboot.org/c/31235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.
I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.
Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
A couple people discussed recently how it's a shame that on some
architectures we can bring up a device but then have nothing to do with
it afterwards. Having payloads to choose from would help a lot there.
Change-Id: Ia66f22947d09afe3076cc2ee12f5b652fe80fc3a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1
should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499
TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
