Remove the Return statement within the PS0, PS3 methods. PS0/3 are not
allowed to return anything. Even an empty return will be resolved to
Return(Null). In order to be conform with the specification, the code
has been refactored to remove the return statements.
Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33293
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of assuming GbE/PDR/EC regions may exist or not, check if there
is a valid region defined in the descriptor and set the region access
permissions based on that.
The net effect change is to enable the use of the PDR region on the
sarien platform, which also uses the GbE and EC regions.
This results in the following example changes:
mb/google/sarien (GbE, PDR, EC)
. DESC BIOS ME GbE PDR EC
-BIOS r rw rw r
-------------------------------
+BIOS r rw rw rw r
mb/google/eve: (no GbE, no PDR, no EC)
. DESC BIOS ME GbE PDR EC
-BIOS r rw rw r
-ME r rw r
-GbE r rw
-EC r rw
-------------------------------
+BIOS r rw
+ME r rw
+GbE
+EC
BUG=b:134703987
Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for the UCSI specification in order to
provide information about the Type-C port and an interface to
perform power and data role swap.
This change is split across the DSDT and SSDT, with the shared
memory and operation region declared in the SSDT after being
allocated in CBMEM.
The OS will fill in the registers in the system memory region and
then call the _DSM method wtih a read or write argument. The DSM
method will copy the required registers to/from the system memory
and the EC and perform the write or read action.
Responses from the EC will generate a new SCI with event code 0x79
which will notify this UCSI ACPI device and the OS driver will take
action to read status from the EC.
BUG=b:131083691
Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The USB Type-C Connector System Software Interface (UCSI) defines a
required memory oregion for the OS UCSI driver to use to communicate
with the BIOS and EC.
This provides a CBMEM ID that can be used by drivers to allocate this
shared memory region for the UCSI driver to use.
BUG=b:131083691
Change-Id: Id5b7fa19436443bc11a6ebe3ce89cd552cee4d85
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SD controller seems to take some time after restarting
the clock at 1.8V before it actually switches from 3.3V to
1.8V. Add a _DSM method that simply sleeps when switching
between 3.3V and 1.8V. Otherwise, the kernel times out too
quickly waiting for the card to acknowledge the 1.8V switch.
The card itself is waiting until it sees the clk signal being
driven at 1.8V.
BUG=b:125441242
TEST=Boot Hatch with SD card and CR2 removed, observe voltage
switch succeeds.
Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signef-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Logs from Linux' i915 suggest that not even the FSP/GOP takes proper
care of this. The sequence is mostly the same as on older platforms,
with a slightly different configuration of the backlight PWM.
We light the panel up with 50% PWM duty cycle. This often results in
an already rather high perceived brightness, but shouldn't be too
blinding.
Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Separate chipset-specific source from sata_init(), and modify it
to better match coreboot conventions. A subsequent patch will
move the generic portion to soc/amd/common.
The support for enabling port multipliers appears to have been
first added for Kabini. Although missing from the documentation,
the ability to affect the HBA Capabilities Register seems to remain
for Stoney Ridge.
Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32660
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the function into common code. Convert it to use the memory-
mapped access type. Convert vboot_platform_is_resuming() to call it
instead of duplicating the source.
BUG=b:131682806
Change-Id: I245bebb8dc2d331cdd56acfb245a004536b792ab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The halt.c file relies on the ACPI register block in the AcpiMmio
range. This register block is consistent across AMD device
generations, so to prepare for moving additional stoneyridge support
to this directory by changing the file name and add a Kconfig symbol
to control the build.
BUG=b:131682806
Change-Id: I2f7442dd78bced7f69b0416a8cd751291f82151f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The banked GPIO functionality in the AcpiMmio block has been consistent
since the Mullins product. Move the basic support into a common
directory.
Each product's pin availability, MUXes, and other details must remain
specific to the product.
The relocated source also drops the weak configure_gevent_smi() that
reports SMI is not available. The stoneyridge port relies on SMI
to do its initialization, similar to modern soc/intel devices. This
is the plan for future soc/amd ports, so make a missing function a
build error instead of a runtime warning.
BUG=b:131682806
Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch makes smm related files compile independent of
ramstage getting compiled.
If user selects RAMPAYLOAD to boot without ramstage, there
will be need for smm code to get compiled independently.
Change-Id: I17a3eb80a4d5ef86e0319357c01b6bf5b90ef15b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Documentation is scarce on the matter, however the related coreboot
code suggests that after the ACK, the keyboard also sends the result
of the self test (passed/failed). It looks like this result is never
consumed here, probably resulting in further confusion for later com-
mands.
Let's revert this for now (if it's not too late for the 4.10 release)
and break things later again. IMHO, due to the fact that there are
dozens of different keyboard controller and keyboard implementations
and no accurate specification followed, such changes should be tested
on a lot of hardware before merge.
This reverts commit a99ed13e33.
This reverts commit 7ae606f57f.
Change-Id: I4d4304d5d8a01e013feac61016c59bcaeea81140
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Kepplinger <martink@posteo.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This automatically detects whether the southbridge supports AHCI.
If AHCI support is selected it will be used unless "sata_no_ahci" is
set in the devicetree to override the behavior.
Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS
region, we had this region set too small, which was causing the
firmware_FMap FAFT test to fail.
BUG=b:133857135, b:129464811
BRANCH=None
TEST=test_that -b hatch <IP> firmware_FMap
Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Initial support for Facebook FBG-1701 system.
coreboot implementation based on Intel Strago mainboard.
Configure 'Onboard memory manufacturer' which must match HW.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701
Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
