Do not use `System Agent version` to refer to the MRC version, which is
what the register being printed contains under normal circumstances. Use
the code from Broadwell, which also happens to be indented with tabs.
Change-Id: I03b24a8e0e8676af7c5297dc3fc7bf60b9bbb088
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit c2ee680 (sandybridge: Use calls rather than asm to call to MRC.)
did it for Sandy Bridge, and this commit does it for Haswell.
Tested on Asrock B85M Pro4, still boots with MRC.
Change-Id: Ic915ae2a30f99805b2c87df8f9a9586a74a40c29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The MRC will perform PCI enumeration, and if it detects a VGA device in
a PEG slot, it will disable the IGD and not reserve any memory for it.
Since the memory map is locked by the time MRC finishes, the IGD can not
be enabled afterwards. Changing this behavior requires patching the MRC.
Hiding the PEG devices from MRC allows the IGD to be used even when a
dedicated graphics card is present. However, MRC will not program the
PEG AFE settings as it should, which can cause stability problems at
higher PCIe link speeds. Thus, restrict this workaround to only run when
the HASWELL_HIDE_PEG_FROM_MRC option is enabled. This allows the IGD to
be disabled and the PEG AFE settings to be programmed when a dedicated
graphics card is to be enabled, which results in increased stability.
The most ideal way to fix this problem for good is to implement native
platform init. Native init is necessary to make Nvidia Optimus usable.
Tested on Asrock B85M Pro4, using the PEG slot with a dedicated graphics
card as well as without. Graphics in both situations function properly.
Change-Id: I4d825b1c41d8705bfafe28d8ecb0a511788901f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45534
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to platform-specific constraints, it is not possible to enable DPR
by programming the MCH's DPR register in ramstage. Instead, assume it
has been programmed earlier and check that its value is valid. If it is,
then simply configure DPR in TXT public base with the same parameters.
Note that some bits only exist on MCH DPR, and thus need to be cleared.
Implement this function on most client platforms. For Skylake and newer,
place it in common System Agent code. Also implement it for Haswell, for
which the rest of Intel TXT support will be added in subsequent commits.
Do not error out if DPR is larger than expected. On some platforms, such
as Haswell, MRC decides the size of DPR, and cannot be changed easily.
Reimplementing MRC is easier than working around its limitations anyway.
Change-Id: I391383fb03bd6636063964ff249c75028e0644cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46490
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While MRC.bin does not allocate any memory for DPR by default, it can be
patched to do so. However, the current northbridge code does not account
for DPR and will, among other things, place CBMEM inside it. Even though
this may seem like a good thing, it renders TianoCore unable to boot and
clashes with Intel TXT support (the reason to enable DPR to begin with).
Update memmap.c so that CBMEM top does not fall within DPR. Also, report
DPR as reserved, so that OSes know that the DPR memory is not to be used.
Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: I74dbd985b980d8a42bfaf2984820005320a803d3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45421
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Several registers have been copy-pasted from i945 and do not exist on
Eagle Lake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: I9582d159aa2344bcf261f0e4b97b15787156f6e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I872269ca3c7fbbcffe83327a20bcf8d98b356beb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Several registers have been copy-pasted from i945 and do not exist on
Ironlake. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I8ac99166a8029dcdbb59028b4a7ee297249de5db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash. If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.
BUG=b:150502246
BRANCH=None
TEST=diff the coreboot.rom files resulting from running
./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
with and without this change to make sure that there was no
difference. Also did this for GOOGLE_CANDY board, which is
baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It primarily contains definitions for MMIO windows. Also, remove
includes from files not directly using the definitions it contains.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: Id28080d9b2924463dd3720492d5e717d65fa0071
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45419
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pre-RAM CBMEM console is tiny. Do not fill it with largely redundant
information, when we could instead store more useful raminit debug logs.
Change-Id: I3a93fdeb67b0557e876f78b12241b70933ad324d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45358
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Several registers have been copy-pasted from i945 and do not exist on
Sandy Bridge. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: I9ad849f57bc68256a2a87ffdc856c4b521e35892
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45357
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Perform the read to the TPM base address using <arch/mmio.h> functions.
Remove dead variable assignment and rename TPM base address macro.
Tested with BUILD_TIMELESS=1. Asus P5QL PRO remains identical.
Change-Id: I11d737903c57fce768b760fe717564dae8879ad0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
