FSP does not set the MSR LT_LOCK_MEMORY when SkipMpInit=1. Therefore,
set LT_LOCK_MEMORY at end of POST, when native MP init is used, to
protect SMM in accordance to Intel BWG.
Test on clevo/cml-u: chipsec says LT_LOCK_MEMORY is locked.
Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure
GPIO pads for audio. However, mainboard is expected to perform all
GPIO configration in coreboot and hence these UPDs must be set to
0. There is no need to expose these UPDs in chip.h and provide
mainboard an option to set these in devicetree.
This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from
chip.h and the corresponding devicetree in mainboards. Currently,
shadowmountain already set these UPDs to 0, whereas adlrvp set these
to 1. But all the ADL boards are correctly configuring the GPIO pads
for audio, so this change should not impact audio for any of these
boards.
BUG=b:183482000
TEST=adlrvp and shadowmountain build successfully.
Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for
cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect
PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus
errors on guybrush.
BUG=b:185514903, b:184356693
TEST=Boot guybrush, observe no port80 codes from PSP
Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 9d4053df:
2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.")
to commit id 57c0c5be:
2021-04-09 11:45:39 +0800 - (cgpt: Move all GPT on SPI-NOR infra behind a flag)
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Id50a892f12ff3c4147c422c98b640ac047143128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52453
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The slot ID can be passed in from the function caller but
parsing slot ID from devicetree is not yet supported and
would still be 0.
Add Slot ID in SMBIOS type 9 for Delta Lake.
Tested=Execute "dmidecode -t 9" to verify.
Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change adds the ATC_REQUIRED flag for the address translation cache
indicator and fixes the devices scope entry in the SATC reporting
structure. The SoC integrated devices in the specified PCI segment
with address translation caches are a type of PCI Endpoint Device.
BUG=None
TEST=Built image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I57b3551f11502da48f3951da59d9426df5a40723
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Nico Huber <nico.h@gmx.de>
When using references to a FieldUnit, DeRefOf is not used when storing a
value into the referenced FieldUnit, only when reading its value.
Tested on out-of-tree Compal LA-A992P, Linux 5.11.15-arch1-2 no longer
spews errors like these in dmesg:
ACPI Error: Needed type [Reference], found [Integer] 000000006cbcc5d8 (20201113/exresop-66)
ACPI Error: AE_AML_OPERAND_TYPE, While resolving operands for [And] (20201113/dswexec-431)
ACPI Error: Aborting method \_SB.PCI0.LPD0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529)
ACPI Error: Aborting method \_SB.PCI0.I2C0._PS0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529)
Change-Id: I60c40452f8b5bdbec76264b578957396de8676ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where
the conditional and dependency are clearly about the presence of
an ACPI NVS table specified by vendorcode. For couple locations also
CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS).
This also helps find some of the CONFIG(CHROMEOS) cases that might
be more FMAP and VPD related and not about ChromeOS per-se, as
suggested by followup works.
Change-Id: Ife888ae43093949bb2d3e397565033037396f434
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config
is for the number of PCIe Clock sources available which is different from PCIe clock reqs.
This is more relevant in alderlake, as the number clock source and clock reqs differ.
However since this is a better name, renaming it throughout the soc/intel tree.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 2c26108208 moved this function to
pmutil.c for Tiger Lake. Do this to all other platforms for consistency.
For Skylake, __SIMPLE_DEVICE__ preprocessor guards are no longer needed.
With this change, pmc.c is only needed in ramstage. Adjust Makefile.inc
accordingly, and drop ENV_RAMSTAGE guards from Skylake.
Change-Id: I424eb359c898f155659d085b888410b6bb58b9ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.
BUG=b:185631878
TEST=Built image and booted to kernel on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I408fac7ff1185f4aa87bc4ffac7f25e31a4802b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- remove unused Kconfig options
- change ACPI device name and HID
- remove ACPI for unused color keyboard backlight
- add support for RGB notification LED
- rename Wifi LED ACPI variable
- set some battery info defaults not populated by the EC
Change-Id: I72eca9deb83e5a6d919d6fcbd3b354fbf6e7a925
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
