It causes fan top speed due to this bug + our board-specific workaround,
and causes invalid temperature sensor readings.
Therefore, re-configure the register "External Temperature Sensor Host
Control Register" to terminate processes when this issue happens.
BUG=chromium:402204
TEST=ran suspend_stress_test 500 times
Change-Id: I439d5de798fbe999e4eec5497e6969b7b453121b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b82f2922c7fce3ca6b2797a8d9775e9db2817fe9
Original-Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219445
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/8820
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The amd/lamar mainboard is the first mainboard to use the f81216h.
These changes are needed to fix up commit 27a63d77 so the
Super I/O builds and functions correctly.
- Wrong #include name
- Removed global variable in romstage
- Missing "case" in switch()
Change-Id: I1b2058a915b776664fba14e4341e8a410b50330f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8255
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the superio code to use printk() on all non-ROMCC
boards.
Change-Id: I23fc307f1346cdb7adaaeccfafe17d9205e909ac
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8113
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Provide proper Makefile and Kconfig components so
that this superio is built as object code. Select
superio component in mainboard Kconfig's to bring
in the link-time symbols and thereby removing the
need for .c inclusion.
N.B. The LPC47N207 Super I/O does not physically exist
on these boards. The Super I/O is found on external LPC
debug card hardware and so should really be made selectable.
However, this is beyond the scope of this specific fix, that
rids us of .c inclusions in romstage.c
Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8084
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.
Change-Id: I44272b4e30a2bc8c3a719df17b837432cd38429c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8083
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.
Change-Id: Ief60d3f54c508cbb7795b284b59710d2c0e3018b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8082
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
There is no Cache As Ram for these boards, let's get rid of them.
Also drop unused dependencies
Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7836
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Hiding pointer types behind 'typedef's is usually not a great
idea at the best of times. Worse the typedef becomes an integer
at different stages in Coreboot. Let us refrain from doing this
at all.
Change-Id: Ia2ca8c98bb489daaa58f379433875864f6efabc8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7136
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The romstage component of Super I/O support is in fact written around
passing a lower and upper half packed integer. We currently have two
typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of
'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the
ramstage context and so is really a conflicting definition. This helps
solve problems down the road to having the 'real' 'device_t' definition
usable in romstage later.
This follows on from the rational given in:
c2956e7 device/pci_early.c: Mixes up variants of a typedefs to 'u32'
Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6231
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE
as argument instead of hard coding and playing funny business with the
pre-processor. Fix board to match.
Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6463
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Remove spurious includes, unused variables and some wasted new lines.
Re-organise things to be consistent with other superio's.
Change-Id: I959bab2f7a83a1b9160d7f010a0de9638b30cf07
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6465
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Provide proper header and function type-signatures for Super I/O
romstage component.
Fix mainboard's bogous romstage component to match.
Change-Id: Icd02199690d0c428b2daadf702d50714dc367692
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5924
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.
Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Pins 41-48 default to being GPIs. This switches the internal
mux to connect them to UARTD.
Change-Id: I61393b8c35cbc664f6520f60eed09ba4bbede0dc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
There was dereference of NULL dev->ops in pnp_enter/exit_conf_mode()
as those calls were made before pnp_enable_devices() was run.
Since hardware did not enter configuration mode, detection failed with
ID and REV read as 0xff.
Change-Id: If13086707cd86e392890ccf4f717e13a87f3317f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5949
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
1. Remove #include .c in romstage.
2. Make romstage component symbols linker-time.
3. Provide header guards and prototypes in superio romstage support.
4. Correct function type-signatures to be static/non-static where
appropriate, avoid 'pretend optimisations' by unnecessarily inlining
functions.
5. Separate out UART enable from various other PNP hard coding
Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5916
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Rewrite smsc/smscsuperio romstage component to be more consistent and
provide header there-by removing #include's of early_serial.c's in
mainboard's.
Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5915
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
