This re-factors clock_get_periph_rate() to be a simpler and also
make a few corrections along the way. To summarize:
- clk_bit_info is no longer used. It had numerous errors and was
really painful anyway since it was just a bunch of opaque magic
numbers that made bugs non-obvious.
- Clock source bitfields for peripherals handled in the switch
statement are 3 bits, not 4. Some divider values are 3 bits,
some are 4. The earlier code always assumed 4 bits for both
which included reserved bits in many cases.
- UART source clock and divider shift values were wrong.
- PWM clock divider was being read from the wrong register.
- SPI3 divider value was being read from the wrong register.
- There was a really confusing calculation for SDMMC0 and SDMMC2
clock rates, but it was never actually used since the switch
statement never handled PERIPH_ID_SDMMC{0,2} and would thus
return if they were ever passed into this function.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b
Reviewed-on: https://gerrit.chromium.org/gerrit/65284
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4463
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This adds a helper function to translate between peripheral clock
select fields in clock source registers and PLLs. Some of this was
already done to handle a few special cases, this generalizes the
earlier work so that follow-up patches can do further clean-up.
Unfortunately, the PLLs represented by clock select fields in
various modules are not uniformly ordered. So for now we focus on
peripheral clock sources only.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff
Reviewed-on: https://gerrit.chromium.org/gerrit/65283
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4462
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Configure the pins for the UART unconditionally in the mainboard code (when we
know which UART to configure) instead of in the UART driver. This also means
the UART will work if later software wants to use it without setting up the
pins.
Built and booted on pit with the serial turned off and some serial init
in the kernel decompression stub fixed.
Change-Id: Icab5755e4f935f52d44b9cb3b43d1cb62acce08f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65299
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This patch implements the basic infrastructure required to use the USB
A-A firmware upload feature on Exynos5 processors with Coreboot. It will
require a corresponding host-side script that activates the feature and
uploads the correct image parts in the correct order to harcoded target
addresses, as described in the comments of alternate_cbfs.c.
Also fixes a bug in the Google Snow mainboard where it would not
correctly initialize the pinmux configuration for the SPI flash bus.
During a normal SPI boot the IROM would already do that for you, but
when booting from USB you have to do it yourself.
Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64875
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4456
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The existing GPIO config routines for SDMMC0-2 are over-generalized
and somewhat confusing as a result. It would work nicely if all SDMMC
ports were configured in the same fashion, but there are a few
exceptions.
For example, the inner function runs differently if we're using 8 bits
of data instead of 4, so a big chunk is skipped for SDMMC2. SDMMC0
requires SD_0_CDn to be an output rather than alternate function and
must have a value set.
This patch trades some verbosity for simplicy. Now the SDMMC GPIO
configuration a straight-forward sequence of GPIO operations
without any exceptions.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: If75075b24c6588c4c1b3be3fb9b1aa95e2fac2d1
Reviewed-on: https://gerrit.chromium.org/gerrit/65248
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4446
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This includes the new dp code, which is better, and the fimd code,
which is changed and improved. We took the chance to remove un-needed
files, and also to remove some foolish u-boot habits, but not all of
them. That will take time.
With these changes we get graphics.
Since the only mainboards we have with 16 bit graphics are 5:6:5,
adjust edid.c to just use that format. If at some future time we need
4:4:4, which seems unlikely, we'll need to add a function to adjust
the lb_framebuffer. Note that you can't just divine this from the EDID,
as the graphics pipe format need not match the actual final format used.
The EDID reading works. We've been requested to support hard-coded
EDIDs and that will come in the next revision. Currently the hard-coded
EDID is ignored for testing.
Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64240
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
In a previous commit the contents of wakeup_need_reset were removed because
the GPIO it referred to wasn't connected to anything on pit. I didn't realize
at that time that that could have been because we hadn't tried getting
suspend/resume working on pit and hadn't updated that file. On snow, the GPIO
is the recovery mode pin. This change updates pit to have the right GPIO,
kirby to read that GPIO, and makes the comments for both pit and kirby more
explicit and spells out the fact that this is the recovery mode GPIO.
Having a check here at all may still be a holdover from snow that isn't
applicable to pit or kirby, but since there is a parallel as far as the
recovery mode GPIO we might as well make them match while waiting for more
information.
Change-Id: Ic1f3f605a0fddf89e8f5668c7a8df30bdfb91d94
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64164
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4421
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
1. Kirby doesn't have a backlight enable GPIO on the AP since that's handled
entirely by the DP-to-LVDS bridge.
2. There is no tps65090 on the other side of the EC who's settings need to be
adjusted. If we need to turn on the LCD or backlight power manually, it will
have to be done in a different way.
3. The PMIC doesn't provide a 32KHz output for the audio codec.
Change-Id: Iadc5f3aec4818805edf3f2517da9e6fee87085dc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63883
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4413
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The function in wakeup.c isn't applicable on kirby. The only constant in
exynos5420.h that was used was the speed of the 4th i2c bus. Instead of having
a whole header file for that one constant used in one place, the constant is
just moved inline along with the comment it had in the header.
Change-Id: I5ad50c5eeaecbbf7865d76afb31a12d36c3371ee
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63882
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4412
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The CBMEM API is different for dynamic CBMEM,
so hide the functions that get in the way (but
our compiler complains about)
Change-Id: I7634a202059548e56c74fe3fe6eff57bc60f1a1b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4546
Tested-by: build bot (Jenkins)
