Add a new mc_ehl variant, which is based on mc_ehl2 implementation.
This patch uses a copy of mc_ehl2 with changes only in naming
as a starting point for the new mc_ehl3 variant.
Follow-up patches will introduce the functional changes against
mc_ehl3.
Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
With commit 0110e1abe0 ("util/genbuild_h: Update printf %d to %s for
sh compatability"), the ChromeOS coreboot build is failing with:
In file included from src/lib/version.c:4:
/build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5473/work/build/nivviks/build.h:10:32: error: 'v1' undeclared here (not in a function)
10 | #define COREBOOT_MAJOR_VERSION v1
| ^~
src/lib/version.c:35:46: note: in expansion of macro 'COREBOOT_MAJOR_VERSION'
35 | const unsigned int coreboot_major_revision = COREBOOT_MAJOR_VERSION;
| ^~~~~~~~~~~~~~~~~~~~~~
/build/nissa/tmp/portage/sys-boot/coreboot-0.0.1-r5473/work/build/nivviks/build.h:11:32: error: 'v9308' undeclared here (not in a function)
11 | #define COREBOOT_MINOR_VERSION v9308
| ^~~~~
src/lib/version.c:36:46: note: in expansion of macro 'COREBOOT_MINOR_VERSION'
36 | const unsigned int coreboot_minor_revision = COREBOOT_MINOR_VERSION;
| ^~~~~~~~~~~~~~~~~~~~~~
This is because the ChromeOS coreboot repo has a tag which is not in the
expected <major>.<minor> format:
$ git tag
v1.9308_26_0.0.22
Change genbuild_h.sh to only use the version from `git describe` if it's
in the expected <major>.<minor> format.
TEST=ChromeOS coreboot build now succeeds, with versions set to 0:
#define COREBOOT_MAJOR_VERSION 0
#define COREBOOT_MINOR_VERSION 0
Building upstream coreboot, the versions are still set correctly:
#define COREBOOT_MAJOR_VERSION 4
#define COREBOOT_MINOR_VERSION 18
Change-Id: I81b2317a83cdec4cc2aad60af2990e5e3f4ad694
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Usha P <usha.p@intel.com>
On nissa, sending EOP late improves boot time by about 57ms.
Before (SOC_INTEL_CSE_SEND_EOP_EARLY):
943:after sending EOP to ME 931,206 (58,431)
943:after sending EOP to ME 932,911 (58,427)
943:after sending EOP to ME 930,908 (58,429)
943:after sending EOP to ME 941,357 (61,748)
943:after sending EOP to ME 933,289 (62,050)
943:after sending EOP to ME 939,578 (62,453)
943:after sending EOP to ME 932,491 (62,050)
943:after sending EOP to ME 929,693 (62,655)
943:after sending EOP to ME 942,247 (62,654)
943:after sending EOP to ME 936,984 (61,751)
After (SOC_INTEL_CSE_SEND_EOP_LATE):
943:after sending EOP to ME 1,107,816 (3,498)
943:after sending EOP to ME 1,053,286 (25,212)
943:after sending EOP to ME 1,124,095 (3,511)
943:after sending EOP to ME 1,098,591 (3,498)
943:after sending EOP to ME 1,107,772 (3,499)
943:after sending EOP to ME 1,080,008 (45,969)
943:after sending EOP to ME 1,081,754 (8,024)
943:after sending EOP to ME 1,109,193 (4,102)
943:after sending EOP to ME 1,088,866 (4,201)
943:after sending EOP to ME 1,081,684 (4,203)
BUG=b:247902068
TEST=EOP time is improved on nissa (measurements above).
Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Utilities like kconfig/conf now will be built inside tests build tree.
It will eliminate possible colisions of target names when using test
framework in more than one place (see CB:70110)
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I4c1eb901c921f4ec6ee8985b154362153c5fd0e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70359
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows for linking selected files with system libc. This
allows for creating libraries interacting with filesystem, standard I/O
and other parts of system. Until now it was only possible using CMocka
proxy functions or functions not masked by code under test.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I652362ba61a25e974d706357fc36479ccee763e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
Increase the default linear framebuffer max height/width for desktops
so that native display resolution works properly on 2160p and 1440p
ultrawide displays.
TEST=build/boot google/fizz, verify libgfxinit display init works
properly on 3440x1440p and 3840x2160p displays.
Change-Id: I95a1f1275a4faea195b73997c648023119807958
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The original value of the `DevIntConfigPtr` is unknown, and there's no
way to be absolutely certain that it actually points to usable memory.
Instead of copying the data, update the pointer's address to reference
the global variable directly. It is assumed that FSP does not write to
the memory pointed by `DevIntConfigPtr`. Confirming this assumption is
pointless; one might as well reimplement FSP instead.
Change-Id: I90594cc09e3fa2aef98658441c323a44a869635b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65217
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This will help to integrate RO SPL table in RO partitions such that it
is used before PSP verstage is loaded. After PSP verstage, SPL table in
RW partition gets used.
BUG=b:243470283
TEST=Build Skyrim BIOS image and boot to OS.
Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support an RPL SKU on lisbon, lisbon must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for lisbon so that it will use the RPL
FSP headers for lisbon.
BUG=b:246657849
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=lisbon emerge-brask intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
flash and boot lisbon to kernel.
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ie60c357ef0a2af2fec90df4a54e56f51ceb927d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Clang generates R_X86_64_32S symbols that get truncated.
TESTED:
- prodrive/hermes boots with GCC and clang
- MTRR are properly cleared (tested by filling in both
MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing)
Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implement native USB initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
TO DO: Figure out how to deal with the FIXME's and TODO's lying around.
Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implement native DMI init for Haswell and Lynx Point. This is only
needed on non-ULT platforms, and only when MRC.bin is not used.
TEST=Verify DMI initialises correctly on Asrock B85M Pro4.
Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There are two ways to control backlight in geralt:
1. MIPI/eDP panel => control backlight via the GPIOs.
(`backlight chip enable` and `PWM dimming control`)
2. eDP OLED panel => enable backlight via `backlight chip enable` and
control dimming over AUX.
For MIPI/eDP panels(#1), both "backlight enable" and "PWM control" GPIOs
will be passed from coreboot. For eDP OLED panel(#2), only the
"backlight enable" GPIO will be passed. If depthcharge successfully gets
the GPIOs, it will use them to control backlight.
BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB
Change-Id: I866fa219722241008e2b0d566b29edf2f6d9321f
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70744
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
dw_i2c_soc_dev_to_bus will return -1 if it failed to find an I2C bus
number for a device. In this case return -1 instead of implicitly
casting the -1 to an unsigned int and passing that as bus number to
dw_i2c_transfer. The dw_i2c_base_address call inside _dw_i2c_transfer
already ended up handling this error case correctly, but better handle
the error more directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06b6005cee0c5c43855cb5b388a9911fc286c984
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
If the temporary nvdata storage inside the vboot context is already
initialized then return immediately without reinitializing from the
backup NV storage. This allows vbnv_init to be called more than once.
Also the check to enable USB Device Controller (UDC) happens after
NVdata is initialized. Hence the nvdata in vboot context can be used
instead of reading from the backup storage again.
BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim.
Change-Id: Id72709e2fc3fe6a12ee96df8df25e55cf11e50a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
