Arthur Heymans
c7eebacbeb
soc/intel/xeon_sp: Tidy up adding MADT ioapic entries
...
Add a helper function to print out debug info and add the MADT entry.
Change-Id: I1a00f87c6edef530c5352929ee9279782be4b112
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com >
2020-11-13 00:24:46 +00:00
Arthur Heymans
83b262275c
soc/intel/xeon_sp: Use a common function to get the IIO HOB
...
TESTED ocp/deltalake still boots.
Change-Id: I69f336c1ff348b8e820340b84494929f2c58ce72
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47296
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-11-12 16:13:49 +00:00
Marc Jones
662ac546fc
soc/intel/xeon_sp: Don't add memory resource twice
...
The resource function is called for each device VID/DID. Only add
the memory resource map from the boot CPU (bus 0) and not for each
socket/CPU. This is a NUMA architecture and has a shared memory map.
All the resources must match across the sockets/CPUs, so they should
only be added to the map once.
Change-Id: Ia336f604441ae8d30b8418300da7c34ab9907cae
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-11-09 10:17:25 +00:00
Marc Jones
5851f9dae5
soc/intel/xeon_sp: Move set_bios_init_completion()
...
Move set_bios_init_completion() and helper functions from skx
and cpx soc_util.c to xeon common util.c. There are some slight
differences between skx and cpx, so used the more correct cpx
functions. Both cpx and skx platforms boot as expected.
Change-Id: Ie416b3a43ccdd14a0eb542786593c2eb4d37450f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47172
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-11-09 10:17:14 +00:00
Arthur Heymans
12985c1dd7
soc/intel/xeon_sp: Look up the IIO_HOB only once
...
The HOB does not move, place its location in .bss.
Change-Id: I2c6dbe4d64138e45fa1dfe7580ffa70d0441bd88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47294
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-11-09 07:44:59 +00:00
Marc Jones
645bca4810
soc/intel/xeon_sp/skx: Reorder soc_util.c
...
Reorder soc_util.c and remove the un-needed #if ENV_RAMSTAGE to match
cpx version in preparation for more de-duplication.
Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-11-09 03:00:45 +00:00
Marc Jones
83729bd430
soc/intel/xeon_sp/skx: Fix MADT CPU indexes
...
The CPU index wasn't getting updated. Confirm MADT sets IOAPIC and CPU
ID numbers.
Change-Id: I72430cc48f4609ac408e723172ba1ed263cca8e3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-11-06 17:05:30 +00:00
Marc Jones
18960ce0c9
soc/intel/xeon_sp: Move CPU helper functions
...
Continue Xeon-SP de-duplication.
Move CPU helper functions from skx/ and cpx soc_util.c to common util.c.
Functions only used by util.c are updated to be static.
The following functions are moved:
int get_threads_per_package(void);
int get_platform_thread_count(void);
const IIO_UDS *get_iio_uds(void);
unsigned int soc_get_num_cpus(void);
void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
void xeonsp_init_cpu_config(void);
Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47170
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-11-06 17:00:14 +00:00
Marc Jones
c6a6e54d05
soc/intel/xeon_sp/cpx: Reorder cpu.c .h includes
...
Clean up the header includes.
Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
2020-11-06 16:59:33 +00:00
Arthur Heymans
1410224cf4
soc/intel/xeon_sp: Use common cpu/intel romstage entry
...
This removes some boilerplate like starting the console and also adds
a "start of romstage" timestamp.
Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-11-05 00:02:07 +00:00
Arthur Heymans
7f44929ed9
soc/intel/xeon_sp: Add a smm_region function
...
This reports where TSEG is located and will be used when setting up
SMM.
Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-11-04 13:43:09 +00:00
Elyes HAOUAS
f0334b86dd
soc/intel/xeon_sp: Convert to ASL 2.0 syntax
...
Change-Id: I43e36f2e736192603be61519d3e185605e81f0e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-11-04 09:43:17 +00:00
Jacob Garber
6df3870012
soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer
...
IIO_RESOURCE_INSTANCE is a large struct, so it should be passed as a
constant pointer rather than making a copy.
Found-by: Coverity CID 1432759
Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46729
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-11-04 09:38:23 +00:00
Arthur Heymans
b38d6bbe1c
soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T
...
The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size.
FSP-M seems to have a very large stack usage so it would overflow
other car symbols located below the coreboot stack such as timestamps
and the pre-ram console, which are now fixed.
TEST: boot with ocp/deltalake.
Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Christian Walter <christian.walter@9elements.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-11-04 08:27:31 +00:00
Marc Jones
2c707160a9
soc/intel/xeon_sp/acpi: Fix uncore dsdt for multiple cpus
...
Fix the asl to use CONFIG_MAX_CPUS to create entries for
multiple cpu uncores. Don't add the RTxx resource entries multiple
times. The function is called for each CPUs.
Change-Id: Ia4eb9716ae4bd72fb4eb98649105be629623cbef
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47060
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-11-03 17:20:23 +00:00
Marc Jones
995a7e25a1
soc/intel/xeon_sp; Use soc specific stack-port function
...
Separate the get_stack_for_port into soc specific functions. This
removes a #if in common code.
Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-11-03 17:18:52 +00:00
Arthur Heymans
087fe9fe27
soc/intel/xeon_sp/bootblock.c: Report the FSP-T output
...
Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46885
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-11-02 06:16:53 +00:00
Marc Jones
70907b00e6
soc/intel/xeon_sp: Call common soc_get_num_cpus()
...
Use a common function to get the number of CPUs for each soc. This
removes a #if for different function names in the common code.
Change-Id: I3348d37fcae72247731e465ec2a65d9583a2f180
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-30 18:55:58 +00:00
Marc Jones
444fda4528
soc/intel/xeon_xp: Combine cpx and skx acpi.c
...
Prepare for common ACPI. Combine cpx and skx acpi.c into a single
file in xeon_sp. This is almost the last step in using common/block
acpi.
Change-Id: I5f40eb7909bb796907682c548219c7515f2ae4d1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46600
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-30 18:55:42 +00:00
Marc Jones
d49c8cfbf1
soc/intel/xeon_sp/skx/acpi.c: Update with cpx changes
...
Prepare for common ACPI. This primarily makes the skx madt table
generation match cpx. There are a few other small changes to remove
unused code and make the files match.
Change-Id: I71a59181226d79c40a4af405653c50c970fb720b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46599
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-30 18:54:10 +00:00
Marc Jones
53b465d1c1
soc/intel/xeon_sp: Move read_msr_ppin() to common util.c
...
Move CPX and SKX read_msr_ppin() to common util.c file.
Update drivers/ocp/smbios #include to match.
Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-30 17:13:53 +00:00
Marc Jones
1f500845b4
soc/intel/xeon_sp: Move common chip.c code
...
Move common CPX and SKX chip.c code to chip_common.c.
Change-Id: I158882ab15659858c2b13b4a3e02a26ef8d4ed3c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-30 17:13:31 +00:00
Marc Jones
9a0d4f8620
soc/intel/xeon_sp/skx: Simplify pci_domain_read_resource
...
Use a simpler pci_domain_read_resource for the stacks. This
makes it the same as the cpx function, since both get the stack
information from the FSP.
This will be merged with common xeon cpx/skx in a later patch.
Change-Id: I0130ce671fe9ff04e48021a0c5841551210aa827
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46308
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-30 17:12:58 +00:00
Marc Jones
0262ffa85c
soc/intel/xeon_sp/skx: Add resource allocator helpers
...
Add and use resource allocator helper functions from cpx. It also
simplifies the allocator by removing IORESOURCE_PCI64 from the resource
type check. It isn't needed since it is an attribute of IO and MEM and
will be added with the appropriate type.
This clean up matches CPX and will help with merging in the future.
Change-Id: I5812b07ba00eeafb4d1e826e9cdf9a659b0248bb
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46306
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-30 17:12:10 +00:00
Marc Jones
8b522db474
soc/intel/xeon_sp: Move function debug macros
...
Move the macros for printing debug information to debug.h in the
common console include directory and device include file.
These are available if the platform selects DEFAULT_CONSOLE_LOGLEVEL_8.
The macros could be used by any platform.
Change-Id: Ie237bdf8cdc42c76f38a0c820fdc92e81095f47c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-29 16:44:19 +00:00
Marc Jones
5b5c52e8de
include/device/device.h: Move resource debug macros
...
Add general debug macros that print resource information.
These are available to select if DEFAULT_CONSOLE_LOGLEVEL_8.
The macros are helpful in debugging complex resource allocation
with multiple buses. The macros are moved from soc/intel/xeon_sp,
where they were originally developed.
Change-Id: I2bdab7770ca5ee5901f17a8af3a9a1001b6702e4
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-29 16:43:00 +00:00
Morgan Jang
bdd863689d
src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7
...
TEST=Execute "dmidecode -t 7" to check if cache error correction type
and cache sram type is correct for each cache level
Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-10-28 10:09:32 +00:00
Morgan Jang
160cb331fc
soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADT
...
Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button
is present on Cooperlake platform.
Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-10-28 10:09:14 +00:00
Jingle Hsu
83a2a007c7
mb/ocp/deltalake: Rename motherboard_fill_fadt()
...
Rename motherboard_fill_fadt() to the common override
mainboard_fill_fadt() function to override FADT.
Tested=On OCP Delta Lake, verify FADT PM Profile is set to
Enterprise Server.
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com >
Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-10-28 02:33:38 +00:00
Elyes HAOUAS
92f46aaac7
src: Include <arch/io.h> when appropriate
...
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-26 06:44:40 +00:00
Marc Jones
d3d50e027f
soc/intel/xeon_sp/acpi: Add pch.asl
...
Add ASL for the PCH. Initially, this only contains
soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL
may be added in the future.
Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45836
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-26 00:15:36 +00:00
Angel Pons
9190345bf0
soc/intel/xeon_sp/skx: Add missing includes
...
Commit 985d956th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46662
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-23 00:49:58 +00:00
Marc Jones
7a25fb8e69
soc/intel/xeon_sp: Rename cpx_generate_p_state_entries()
...
Prepare for common ACPI. Rename cpx_generated_p_state_entries()
to the common soc_power_states_generation() function. Add
empty soc_power_states_generation() to skx.
Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-22 21:36:40 +00:00
Marc Jones
3fc04842cb
soc/intel/xeon_sp/skx: Move skx specific FADT setting
...
Prepare for common ACPI. Move the skx specific FADT settings
from acpi.c to soc_acpi.c, soc_fill_fadt. This gets acpi_fill_fadt()
to match common/block/acpi.c.
Change-Id: I04873d13d822de514acbb58501171285bd5b020e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-22 21:35:45 +00:00
Marc Jones
521a03f303
soc/intel/xeon_sp: Move uncore_inject_dsdt() call
...
Prepare for common ACPI code. Move uncore_inject_dsdt() to the
uncore device acpi_inject_dsdt call.
Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-22 21:35:11 +00:00
Marc Jones
8066fda9ed
soc/intel/xeon_sp: Move ACPI prototypes from chip.h
...
Prepare for common ACPI. Move the soc ACPI function prototypes from
cpx and skx chip.h to include/soc/acpi.h.
Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-10-22 21:34:29 +00:00
Marc Jones
8972750b26
src/soc/intel/xeon_sp/skx: Update get_iiostack_info()
...
Add Pci64BitResourceAllocation return value to get_iiostack_info().
This matches cpx function and is used in future de-duplication.
Change-Id: I939c0101c751d9afced4ab33487958b93e59924c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46307
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-22 21:30:57 +00:00
Marc Jones
985d956833
soc/intel/xeon_sp/skx/: Clean up soc_util.c
...
Remove unused c_util.c helper functions and clean up soc_util.h in
preparation for merging common code with cpx/.
Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-22 17:03:49 +00:00
Marc Jones
97321db21d
soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.c
...
De-duplicate and prepare for common ACPI. Move common
northbridge ACPI code to nb_acpi.c. There are a few
differences between the skx and cpx defined FSP hob names
and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)).
Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-10-22 16:28:16 +00:00
Marc Jones
2560ad3233
soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt()
...
Prepare for common ACPI code. Make acpi_fill_fadt() match
intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt()
to set cpx fadt->flags.
Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-22 16:18:11 +00:00
Michael Niewöhner
f50ea988b0
soc/intel,mb/*: get rid of legacy pad macros
...
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-10-21 07:16:01 +00:00
Marc Jones
b9365ef377
soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cb
...
platform_fsp_silicon_init_params_cb is called by the fsp driver and
calls mainboard_silicon_init_params which sets the mainboard
PCH GPIOs.
Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-19 01:35:50 +00:00
Marc Jones
e1db55b43e
soc/intel/xeon_sp: Add get_system_memory_map()
...
Prepare for common ACPI. Add get_system_memory_map() helper
function to soc_util.c and use it in the SRAT ACPI code
to match the cpx code.
Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-15 15:55:25 +00:00
Marc Jones
3c667a2e7d
soc/intel/xeon_sp: Use generic config_t
...
Don't use the silicon-specific struct type to get common config
options. Instead, use the generic config_t typedef. This allows
the function to be moved to common code in upcoming patches.
Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46057
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-09 20:27:31 +00:00
Christian Walter
19df8d85e0
soc/intel/xeon_sp: Set CPU_ADDR_BITS to 46 for SKX and CPX
...
According to document number 338846 and 336062 this should be set to 46 bits.
Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59
Signed-off-by: Christian Walter <christian.walter@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
2020-10-09 16:25:11 +00:00
Jonathan Zhang
1c3fef2ca9
soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack
...
Without skipping of DRHD generation for non-PCIe stack, the OS
kernel detects incorrect DMAR table with following messages:
[ 0.561817] Your BIOS is broken; DMAR reported at address 0
Signed-off-by: Jonathan Zhang <jonzhang@fb.com >
Change-Id: I098605daf12a264f390613581427ec722afcddaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-10-09 16:24:43 +00:00
Christian Walter
abb3757847
soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMX
...
Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4
Signed-off-by: Christian Walter <christian.walter@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45869
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-08 15:38:28 +00:00
Johnny Lin
7581352759
soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
...
For now only implement for one socket and some of the fields
are hard-coded for DDR4 including memory device type, data width
and ECC support.
Change-Id: I3cb72d18027d972140828970206834ff55b72022
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-10-08 12:09:26 +00:00
Jonathan Zhang
431741bf00
soc/intel/xeon_sp/cpx: correct GSI bases for IO APICs
...
With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct
the coreboot assignment of GSIs for IO APICs.
Without this patch, there are following target OS boot messages:
[ 1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119]
After this patch, the boot messages are:
[ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127
Also without this patch, there is boot stability issue. About one in
20 reboots, the target OS fails to boot with following failure:
[ 4.325795] mce: [Hardware Error]: Machine check events logged
[ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a
[ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086
[ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d
The MCE error happens in bank 9. The Model specific error code
shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means
something goes wrong when cache write back to mmio. It is a generic
transaction type error in level 2.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com >
Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45941
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Christian Walter <christian.walter@9elements.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-08 12:05:02 +00:00
Marc Jones
301c7e67bf
soc/intel/xeon_sp/skx: Move get_srat_memory_entries()
...
Prepare for common ACPI code.
Move get_srat_memory_entries() from soc_util.c to soc_acpi.c where
the other srat ACPI functions are located.
Change-Id: If26641497e1c16d5cf493490711aa08d6e1cb640
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45846
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-10-06 15:27:14 +00:00
