Commit Graph

15 Commits

Author SHA1 Message Date
Kyösti Mälkki
8abf66e4e0 cpu/x86: Flip SMM_TSEG default
This is only a qualifier between TSEG and ASEG.

Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09 12:48:46 +00:00
Julien Viard de Galbert
cf2b72f951 soc/intel/denverton_ns: Enable ACPI using intelblock
- Port the existing denverton tables to intelblock
- Add C-States table for denverton

Note: Removed code is functionally identical to corresponding
common code.

Tested-on: scaleway/tagada

Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25 11:24:30 +00:00
Vanessa Eusebio
cd97982e2e soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE

Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5
Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
Reviewed-on: https://review.coreboot.org/c/26928
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18 08:16:28 +00:00
Nico Huber
1d748c5346 console: Change BOOTBLOCK_CONSOLE default to y
Invert the default instead of selecting it everywhere. Restores the
ability to use its Kconfig prompt.

Beside Qemu targets, the only platforms that didn't select it seem
to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The
latter two were about to be patched anyway.

Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30891
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 12:13:55 +00:00
Nico Huber
3eb720c36e drivers/uart/Kconfig: Be smarter about DRIVERS_UART_8250IO
It defaults to y to avoid having to select it per mainboard. But that
makes a mess because it results in linker conflicts unless other UART
drivers disable it explicitly.

We try to be smarter about the default value for now. The real solu-
tion would be to hardcode it per mainboard. But who knows which boards
actually have it?

Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29571
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-20 17:48:30 +00:00
Nico Huber
371a6674ac soc/intel/.../Kconfig: Move GPIO debug option into debug menu
Rename DEBUG_SOC_COMMON_BLOCK_GPIO to DEBUG_GPIO and move it into the
Debugging menu.

Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-11-18 21:20:58 +00:00
Elyes HAOUAS
9d917f67fe soc/intel/denverton_ns/Kconfig: Remove unused HSUART_FUNC
Change-Id: I1ec6f0687083c17314588c85af289b4b27c5441c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29598
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:00:00 +00:00
Patrick Rudolph
f677d17ab3 intel: Use CF9 reset (part 2)
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().

Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.

We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.

Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.

Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-22 08:35:32 +00:00
Julien Viard de Galbert
2912e8e5dc soc/intel/denverton_ns: Enable common block PMC
Mainly update headers to build.

Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.

Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-14 14:11:03 +00:00
Stefan Tauner
ef8b95745f src/*/intel/: clarify Kconfig options regarding IFD
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.

Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.

Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.

Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-13 08:25:31 +00:00
Kyösti Mälkki
730df3cc43 arch/x86: Make RELOCATABLE_RAMSTAGE the default
No need to provide an option to try disable this.

Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.

Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06 12:29:19 +00:00
Julien Viard de Galbert
5a1f5400fb soc/intel/denverton_ns: Enable common code for CPU
Change-Id: Ib215aa17dd20112946b74a1b63ce8a735388873c
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24927
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14 21:03:43 +00:00
Julien Viard de Galbert
3ac3a68eef soc/intel/denverton_ns: port gpio to intelblock
The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.

Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14 21:03:17 +00:00
Subrata Banik
74558813c0 drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driver
Now SOC code can select the require UDK support package for any
platform going forward with FSP2.0 model.

Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31 05:56:19 +00:00
Mariusz Szafranski
a404133547 soc/intel/denverton_ns: Add support for Intel Atom C3000 SoC
This change adds support for Intel Atom C3000 SoC
("Denverton" and "Denverton-NS").
Code is partially based on Apollo Lake/Skylake code.

Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-05 13:39:54 +00:00