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Author SHA1 Message Date
Karthikeyan Ramasubramanian
f354c8c625 mb/google/dedede: Configure WLAN 
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device.
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN - both CNVi and M.2.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-03-14 23:31:05 +00:00
Karthikeyan Ramasubramanian
136e0cbbc1 mb/google/dedede: Add BT Disable GPIO configuration 
Disable the BT module in bootblock and enable it in ramstage. This
allows for loading the BT firmware during reboot.

TEST=Build and boot the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-14 23:29:30 +00:00
Eric Lai
f9c6a8821f mb/google/drallion: Enable GEO SAR 
Enable GEO SAR function.

BUG=b:150347463
BRANCH=drallion
TEST=NA

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-14 23:28:06 +00:00
Wonkyu Kim
c04757b108 mb/intel/tglrvp: Update GPIO setting 
Update GPIO reset type from PLTRST to DEEP.
DEEP setting is more conservative for S3/S4/S5.
Detail information is bug.

BUG=b:151305120
TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie7d08560ea2ef3623bbd4734b30c80e707869c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39476
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-14 23:27:00 +00:00
Prashant Malani
dabc0adb3a ec/google/chromeec/acpi: Move ECPD under CREC 
Move the ECPD (GOOG0003) device under CREC (GOOG0004) so that the ECPD AP
device drivers can access the parent EC device to communicate with the
EC. Also, update the Notify() call to reflect the new location of the
ECPD device.

Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-03-14 02:42:35 +00:00
Srinidhi N Kaushik
22d5b07160 mb/google/volteer: Enable Audio DSP UPD 
Provide settings for configuring the link between HD-Audio controller
and display unit for purposes of HDMI/DP Audio playback.

BUG=b:144708516, b:148385924
TEST=none

Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-13 18:31:17 +00:00
Edward O'Callaghan
6daa8c3ba5 mb/google/hatch/Kconfig: Disable VBOOT_EARLY_EC_SYNC on Puff 
Early ec sync needs to be disabled for EFS2 to function.

BUG=b:151115320
BRANCH=none
TEST=none

Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-03-13 02:50:21 +00:00
John Zhao
49111cd2ba soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table 
Tigerlake platform supports Virtualization Technology for Directed I/O.
Enable VT-d feature and generate DMAR ACPI table.

BUG=None
TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI
remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and
"iasl -d DMAR" to check all entries.

Change-Id: Ib89d0835385487735c63062a084794d9da19605e
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
 2020-03-12 21:36:57 +00:00
Patrick Georgi
a7ec42619c soc/intel/*/smihandler: Only compile in TCO SMI handler if needed 
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help
the linker throw out the function that handles them in that case.

Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Michael Niewöhner
 2020-03-12 21:36:20 +00:00
Pandya, Varshit B
4f8b00602c mb/google/dedede: Enable trackpad support 
1. Configure trackpad interrupt GPIO.
2. Set i2c0 configuration.
3. Add trackpad ACPI support.

TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz
on trackpad operation.

Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-03-12 07:41:25 +00:00
raymondchung
d1f3022ebf mb/google/hatch: Create nightfury variant 
Create new variant and build for nightfury.

BUG=b:149226871
TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage

Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
 2020-03-12 07:41:10 +00:00
Wonkyu Kim
396bb46e7d mb/google/volteer: configure L1Substate for PCIe 
Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.

Reference: #613582 Tiger Lake PCH-LP Sightings Report
           issue id #1409566330

BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2020-03-12 07:40:45 +00:00
Wonkyu Kim
84b4882b99 soc/intel/tigerlake: Configure L1Substates for PCH Root ports 
Set value for PcieRpL1Substates according to devicetree.

Chip config parameter PcieRpL1Substates uses (UPD value + 1)
because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
In order to ensure that mainboard setting does not disable L1 substates
incorrectly, chip config parameter values are offset by 1 with 0 meaning
use FSP UPD default.

get_l1_substate_control() ensures that the right UPD value is set in
fsp_params.

Chip config parameter values
0: Use FSP UPD default
1: Disable L1 substates
2: Use L1.1
3: Use L1.2 (FSP UPD default)

BUG=none
BRANCH=none
TEST=Boot up and check FSP log for PCIe config for this values

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-12 07:40:11 +00:00
Joel Kitching
9a2922871d vboot: remove extraneous vboot_recovery_mode_memory_retrain 
Just call get_recovery_mode_retrain_switch() directly.

BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Icb88d6862db1782e0218276984e527638b21fd3a
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-12 07:39:47 +00:00
Srinidhi N Kaushik
18129f919a soc/intel/tigerlake: Enable HDA through dev_enabled 
Check for dev enabled status for HDA controller and
update the UPD accordingly.

BUG=151174264
BRANCH=none
TEST=Build and boot tglrvp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39441
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-12 07:38:50 +00:00
Karthikeyan Ramasubramanian
6f785b0f62 mb/google/dedede: Add ACPI configuration for USB ports 
Enable USB ACPI driver. Add ACPI configuration for all the USB ports.
Since one of the USB ports is used for Bluetooth configure the
reset_gpio used by that port.

TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
 2020-03-11 19:58:06 +00:00
Wonkyu Kim
f787e87145 mb/intel/tglrvp: Enable Hybrid storage mode 
BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
 2020-03-11 19:57:44 +00:00
Michael Niewöhner
ccde6be13a soc/intel/common/block/smm: add case intrusion to SMI handler 
This adds case intrusion detection to the SMI handler. At this point one
can add the code to be executed when the INTRUDER signal gets asserted
(iow: when the case is opened).

Examples:
 - issue a warning
 - trigger an NMI
 - call poweroff()
 - ...

Tested on X11SSM-F.

Change-Id: Ifad675bb09215ada760efebdcd915958febf5778
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-03-11 15:36:31 +00:00
Meera Ravindranath
5f26d8cb4a mb/google/dedede: Add SPD hex file for Samsung memory part 
BUG=b:150154457
BRANCH=none
TEST=Build dedede, flash and boot to kernel.

Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-11 15:12:46 +00:00
Patrick Rudolph
cb858d6d62 superio/nuvoton/nct5539d: Update documentation and remove DSDT 
There seems to be no board using this, but some currently under review.
Remove the DSDT, which doesn't work together with the SSDT ACPI
code generation. Also update the documentation pointing to the SSDT
generator.

Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-11 15:03:39 +00:00
Patrick Rudolph
6dc488a678 drivers/intel/gma/acpi: Prevent DivideByZero error 
In case backlight control isn't enabled BCLM is zero.
Return early instead of running into a DivideByZero error.

This happens on devices that don't have backlight control, like
desktops and servers. The proper fix is to not include those
ACPI methods, but that requires a much bigger refactoring.

Change-Id: Ie9bdb00949d6d44fd99321db556d6008d2d12a7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-11 14:50:35 +00:00
Jamie Ryu
a02f00e5d6 soc/intel/tigerlake: Save DIMM info by available nodes 
TEST=Verified that dmidecode produces output identical to private repo

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-11 14:43:25 +00:00
Sumeet Pawnikar
fe2a4c1001 mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C 
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.

BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.

Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
 2020-03-11 14:42:13 +00:00
raymondchung
6bc471461b mb/google/hatch: Add LP_4G_2133 SPD 
Add LPDDR3 4GB 2133MHz SPD file.

BUG=b:149226871
TEST=Build and check cbfs has the spd.bin

Change-Id: I1598774a87eecc76082286540beadaa3c26eda69
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-11 14:41:05 +00:00
Venkata Krishna Nimmagadda
c34bb3807c mb/google/volteer: Enable pcie rp11 for optane 
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.

Configuring pciecontroller3 to be set from 2x2.  This will by done by
auto detecting optane memory: enabling HybridStorageMode.


BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'

Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-11 14:39:06 +00:00
Ronak Kanabar
35d7843799 soc/intel/tigerlake: Correct FSP log interface 
select correct UART settings according to Kconfig
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART

Add check for DEBUG_INTERFACE_TRACEHUB selection and set
"PcdDebugInterfaceFlags" UPD accordingly.

BUG=None
TEST=boot jslrvp board with Debug FSP and check FSP UART log
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
 2020-03-11 14:38:17 +00:00
Karthikeyan Ramasubramanian
840bef061f soc/intel/tigerlake: Fix stale device pointer usage 
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I43cccd32589d75a9b0c7e60f8c82b19bbe6b69a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
 2020-03-11 14:37:28 +00:00
Alex Levin
a53dbd4780 mb/google/volteer: Disable WWAN PCIe 
Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer.

BUG=b:146226689
BRANCH=none
TEST=lsusb shows WWAN device

Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-03-11 14:37:01 +00:00
Elyes HAOUAS
0965044c99 commonlib/cbfs.c: Remove unused macro 
Change-Id: I330de4357fa48ee3d76a97a682b389ef42e7a135
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-11 14:36:45 +00:00
Elyes HAOUAS
04e0712f46 Treewide: Add some gcc's warning options 
Change-Id: I789c8906542c59477b0037d39e7aa4fb2dcf22c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2020-03-11 14:36:24 +00:00
Wonkyu Kim
66815114cf mb/intel/tglrvp: sync up variant folders with latest up3 
During intial UP4 patch, below UP3 patches merged which should be
applied for UP4.
https://review.coreboot.org/c/coreboot/+/39201
https://review.coreboot.org/c/coreboot/+/39229
Merge these patches to UP4

BUG=none
BRANCH=none
TEST=Build TGL UP4

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I7b24cb2b0d03309cf67c6c21ddc2031a054f6110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
 2020-03-11 14:33:16 +00:00
Michael Niewöhner
2bd2be545f soc/intel/common/block: tco: enable intruder SMI if selected 
Set TCO to issue an SMI when the case instrusion switch gets pressed.

The SMI is controlled along with the general TCO SMI Kconfig.

Tested on X11SSM-F.

Change-Id: I3bc62c79ca3dc9e8896d9e2b9abdc14cfa46a9e7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-03-11 14:28:53 +00:00
Evgeny Zinoviev
fc59f0860b Documentation: Fix a typo 
filse -> files

Change-Id: Iaf0c3a064b42dde70b1e01cfc15ad3187bf8bfcc
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
 2020-03-11 14:28:34 +00:00
Elyes HAOUAS
9006df98c7 mb/biostar/am1ml: Remove old reference to olivehillplus 
Change-Id: I219fb2c12bb865288364f6e48b1e3d64c14bc036
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-11 14:27:07 +00:00
Elyes HAOUAS
e3a1386694 mb/asus/am1i-a: Remove old reference to olivehillplus 
Change-Id: Idfb8c834ae63226546a4e2860d9b206ba0288718
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-11 14:27:02 +00:00
Elyes HAOUAS
149620fdfd mb/amd/olivehillplus: Drop unmaintained ROMCC board 
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Ie79637c992874bd06009ed9b3e9f470b44e749b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39064
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-11 14:26:38 +00:00
Elyes HAOUAS
3002eb42ed mb/amd/bettong: Drop unmaintained ROMCC board 
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: I1bce09ba5041a6636f900de611846467653f35a9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-11 14:26:35 +00:00
Elyes HAOUAS
f4cfefe788 mb/amd/db-ft3b-lc: Drop unmaintained ROMCC board 
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Ib4a95c650cc4d1cddc2ba530c12ce448a1943b34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-11 14:26:12 +00:00
Elyes HAOUAS
e13bc1c12c mb/amd/lamar: Drop unmaintained ROMCC board 
Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Iaa812dc66ddc14c24263a68e73115502ba5e2417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-11 14:26:06 +00:00
Elyes HAOUAS
8273e13a11 intel/i945: Call fixup_i945_errata() only for mobile version 
Per Mobile Intel ® 945 Express Chipset Family - Specification Update
Document Number: 309220-013 (page 15), the power saving optimization
Erratum is for Mobile Intel ® 945 Express Chipset family.

So rename 'fixup_i945_errata()' to 'fixup_i945gm_errata()' and apply
that function only for I945GM.

Change-Id: I2656021b791061b4c22c0b252656a340de76ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-11 14:25:46 +00:00
Julius Werner
8355aa4de2 prog_loaders: Remove CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING 
This option is not used on any platform and is not user-visible. It
seems that it has not been used by anyone for a long time (maybe ever).
Let's get rid of it to make future CBFS / program loader development
simpler.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2fa4d6d6f7c1d7a5ba552177b45e890b70008f36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2020-03-11 12:32:24 +00:00
Julius Werner
1645ecc8f6 cbfs: Remove unused functions 
cbfs_boot_load_stage_by_name() and cbfs_prog_stage_section() are no
longer used. Remove them to make refactoring the rest of the CBFS API
easier.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie44a9507c4a03499b06cdf82d9bf9c02a8292d5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2020-03-11 12:31:28 +00:00
Kangheui Won
5674bf15f9 mb/google/puff: Enable cros_ec_keyb device 
This is required to transmit button information from EC to kernel.

BUG=b:150830342
BRANCH=None
TEST=firmware_ECPowerButton test passes on puff

Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
 2020-03-11 06:29:31 +00:00
Bartek Pastudzki
69a88ddb5d util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format 
Intel supplies microcode (at least for MinnowBoard) in Intel Assembly
*.inc format rather than C header. This change allow to pass in
configuration directory with *.inc files rather than list of *.h
files.

Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540
Signed-off-by: Bartek Pastudzki <Bartek.Pastudzki@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-10 20:50:12 +00:00
Nico Huber
47ac6355b3 soc/intel/common: Add more GPIO definition macros 
Make i/o-standby state and termination configurable for GPIs.

Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-10 20:47:10 +00:00
Stephen Douthit
56a74bca69 soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling 
This code also sets unused interrupt lines to the recommended safe
value of 0xff instead of ignoring such devices.

Change-Id: I7582b41eb3288c400a949e20402e9820f6b72434
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-10 20:45:53 +00:00
Stephen Douthit
ecb0e409a4 soc/intel/dnv: Add ACPI _PRT methods for virtual root ports 
This eliminates Linux kernel warnings that look like:
    pcieport 0000:00:17.0: can't derive routing for PCI INT B
    ixgbe 0000:07:00.1: PCI INT B: no GSI - using ISA IRQ 10

Change-Id: I2029e7a8252b9e48c1df457d8da5adce7d1ac21d
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-10 20:45:40 +00:00
Stephen Douthit
a51f490870 soc/intel/dnv: Fix ACPI reporting of root port interrupt routing 
pcie_port.asl defines an IRQM method that looks up legacy interrupt
swizzling based on incoming interrupt "pin" A-D and root port number.

Unfortunately the 8-bit root port number stored at offset 0x4F in the
config space matches the device number, not the 1-8 scheme used in
the LUT reported to the OS.

Fix the case values to match the hardware.

Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-03-10 20:45:34 +00:00
Praveen Hodagatta Pranesh
aa6a8fb919 mb/intel/{saddlebrook,kunimitsu}: Add macro for SaGv config 
Change-Id: Ia31da9997ba46c15cd385bf55e009cf299848b64
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36423
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-10 20:42:14 +00:00
Elyes HAOUAS
b7731574f4 src: Remove unneeded 'include <arch/cache.h>' 
Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-03-10 20:39:50 +00:00