74d7192f22
mb/google/dedede/var/pirika: Support for Samsung K4U6E3S4AB-MGCL
...
Add the new memory support:
Samsung K4U6E3S4AB-MGCL
BUG=b:294151054
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run ./util/spd_tools/lp4x/gen_part_id.go JSL lp4x \
src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76542
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-04 03:50:48 +00:00
86f4f2fb34
cpu: Get rid of CPU_SPECIFIC_OPTIONS
...
Remove dummy CPU_SPECIFIC_OPTIONS.
Change-Id: I267b2a7c6dfc887b572e1b63b0f59fbfa4d20f0e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76681
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-04 03:00:25 +00:00
33201ab49f
docker/coreboot-sdk/Dockerfile: Remove old workaround
...
Remove old workaround for automake and aclocal.
Change-Id: Ifc00a479fd08d9ee4d97df6da8762bae2d097827
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-08-03 18:36:35 +00:00
fda10a44b6
util/docker: Remove manual symlink python3 to python
...
Debian sid symlinks already python3 to python.
Change-Id: Ibc3b2b047df7e1066624d4dd8aa9664ab1869222
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-08-03 18:35:46 +00:00
d2e7c0f30d
drivers/intel/gma/Kconfig: Remove unused INTEL_GMA_OPREGION_2_0
...
Change-Id: I9241d713fb8cc26c768746c8e442b46292036d20
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76694
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 18:34:11 +00:00
06cb756f02
soc/intel/common/block/cse/Kconfig: Remove unused symbols
...
Change-Id: I35742721e049102a3e153b857824073a5d257cc3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76693
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 18:33:56 +00:00
93eeb299c4
soc/intel/xeon_sp/spr/Kconfig: Remove unused MAX_MC_CHN
...
Change-Id: Ia4011a0f29d360fbe46a5e052e2acb3d23d8ceaf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76695
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 18:33:21 +00:00
80af4b3ea1
mb/ibm/sbp1/Kconfig: Remove unused MAX_SOCKET_UPD
...
Change-Id: I5d9133f2255a96c8367f69dcbb198a1a142cdb82
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-08-03 18:32:42 +00:00
09f7d67c9a
soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONS
...
Change-Id: I5ad1a1bf51bb7a451239252f01a90c1d4d94ba49
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76685
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 18:29:42 +00:00
2e52f0e243
soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONS
...
Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-08-03 18:29:27 +00:00
a56a5c2cf8
soc/intel/tigerlake: Remove dummy CPU_SPECIFIC_OPTIONS
...
Change-Id: Id268943b9347fdb54e07b55c0a2a18ac77bb3a58
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-08-03 18:27:42 +00:00
ef959b72bc
soc/intel/xeon_sp/Kconfig: Remove useless USE_FSP2_0_DRIVER
...
Change-Id: Ic384ee804e217ba79f7e191f122ec61565abfc40
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-08-03 18:26:28 +00:00
24548e4c56
soc/intel/xeon_sp/spr/Kconfig: Remove unused SIPI_FINAL_TIMEOUT
...
Change-Id: I915e0e942adf33175fdc9fe055fce013824d6c0f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76698
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 18:25:23 +00:00
4bf1385c6c
soc/intel/broadwell/Kconfig: Remove dummy SOC_SPECIFIC_OPTIONS
...
Change-Id: I4ccb8d38f18cb440f54723cc1f29e25b82dac8ee
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76700
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 18:24:26 +00:00
ede988fb53
Makefile.inc: Fix typo in comment
...
Replace FILANAME with FILENAME.
Change-Id: I96388245df406e6b4cb1cd3418f6a32d5b23499f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76890
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 18:20:39 +00:00
6e133fa470
linux_trampoline: Handle 64-bit framebuffer addresses
...
To support full 64-bit addresses, there is a new field `ext_lfb_base`
since Linux 4.1. It is unclear, however, how a loader is supposed to
know if the kernel is compatible with this. Filling these previously
reserved bits doesn't hurt, but an old kernel would probably ignore
them and not know that it's handling a clipped, invalid address. So
we play safe, and only allow 64-bit addresses for kernels after the
2.15 version bump of the boot protocol.
Change-Id: Ib20184cf207f092062a91ac3e6aa819b956efd33
Signed-off-by: Nico Huber <nico.h@gmx.de >
Co-authored-by: Bill XIE <persmule@hardenedlinux.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76479
Reviewed-by: Bill XIE <persmule@hardenedlinux.org >
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 17:55:01 +00:00
6a50e555fc
util/abuild: Add per-build statistics tarfile
...
Change-Id: Icb9a5bdf94013fe493dc8ec634cf3094bcff2838
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75803
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2023-08-03 15:21:22 +00:00
572db7f4c7
mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part
...
Add pirrha supported memory parts in mem_parts_used.txt, generate
SPD IDs for them.
1. K3KL8L80CM-MGCT (Samsung)
2. K3KL6L60GM-MGCT (Samsung)
BUG=b:292134655
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage
Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76881
Reviewed-by: Derek Huang <derekhuang@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 15:09:57 +00:00
10bd2a27b9
soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
...
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize
when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs
are programmed only when INTEL_TME is enabled.
Bug=b:276120526
TEST=Able to build REX platform.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com >
Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 14:18:49 +00:00
62ceabc4d1
soc/intel/common: Merge TME new key gen and exclusion range configs
...
Merge TME_KEY_REGENERATION_ON_WARM_BOOT and
TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option
named TME_KEY_REGENERATION_ON_WARM_BOOT.
Program Intel TME to generate a new key for each warm boot. TME always
generates a new key on each cold boot. With this option enabled TME
generates a new key even in warm boot. Without this option TME reuses
the key for warm boot.
If a new key is generated on warm boot, DRAM contents from previous
warm boot will not get decrypted. This creates issue in accessing
CBMEM region from previous warm boot. To mitigate the issue coreboot
also programs exclusion range. Intel TME does not encrypt physical
memory range set in exclusion range. Current coreboot implementation
programs TME to exclude CBMEM region. When this config option is
enabled, coreboot instructs Intel FSP to program TME to generate
a new key on every warm boot and also exclude CBMEM region from being
encrypted by TME.
BUG=b:276120526
TEST=Able to build rex.
Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 12:56:10 +00:00
bc1533e089
mb/google: Add more comment on GFX devices for the future reference
...
Add more details to instruct future boards/models implementers regarding
how GFX devices should be added.
If HDMI and DP connectors are enumerated by the kernel in
/sys/class/drm/ then corresponding GFX device should be added to ACPI.
It is possible that some connectors do not have dedicated ports, but
still enumerated.
The order of GFX devices is DDIA -> DDIB -> TCPX.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224
Signed-off-by: Won Chung <wonchung@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jakub Czapiga <jacz@semihalf.com >
2023-08-03 12:54:31 +00:00
f232b19e56
mb/google/nissa/var/craaskov: Add overridetree
...
Add override devicetree based on schematics(ver. 20230714).
BUG=b:290248526
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76662
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-by: Derek Huang <derekhuang@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 12:53:18 +00:00
9ec479de47
soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properly
...
Build issue introduced by patch CB:76418 (commit hash
01025d3ae7michal.zygowski@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-03 11:19:13 +00:00
eeba3e7915
src/soc/intel/alderlake: add SOC_INTEL_RAPTORLAKE_PCH_S symbol
...
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected
by board with RPL-S PCH.
For now only the IoT variant of RPL-S FSP is available for use with
700 series chipsets. Boards with 600 series chipsets can still use
RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU
support.
Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-08-03 10:10:17 +00:00
01025d3ae7
soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
...
Only the headers on Intel FSP repository have the CnviWifiCore
present. Options guarded for RPL like: DisableDynamicTccoldHandshake
or EnableFastVmode and IccLimit is also supported by all public FSPs
(except ADL-N for the handshake).
Options like LowerBasicMemTestSize and DisableSagvReorder have to be
guarded when FSP_USE_REPO is not selected, as publci FSPs do not have
these options.
Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE
as dependency on the guarded UPDs to make them available for FSPs
that support them as well. Also prioritize the headers from FSP repo
over vendorcode headers if FSP_USE_REPO is selected.
Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com >
2023-08-03 09:55:19 +00:00
ce7d818254
MAINTAINERS: Add a maintainer for soc/intel/meteorlake and mb/google/rex
...
Signed-off-by: Eran Mitrani <mitrani@google.com >
Change-Id: I7f01ee979036071ce7574254101e25b908f8e788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2023-08-03 04:30:25 +00:00
a07b09ab71
acpi.c: Find FACS using 64bit address fields
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I406b9b470d6e76867e47cfda427b199e20cc9b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2023-08-03 01:41:54 +00:00
d8f2dcebd8
acpi.c: Swap XSDT and RSDT for adding/finding tables
...
If ACPI is above 4G it's not possible to have a valid RSDT pointer in
RSDP, therefore swap RSDT and XSDT. Both are always generated on x86.
On other architectures RSDT is often skipped, e.g. aarch64. On top of
that the OS looks at XSDT first. So unconditionally using XSDT and not
RSDT is fine.
This also deal with the ACPI pointer being above 4G. This currently
never happens with x86 platforms.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I6588676186faa896b6076f871d7f8f633db21e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-08-03 01:41:40 +00:00
a9b08f2b61
mb/google/rex/variants/ovis: Use and configure RT8168 driver
...
This makes sure google/ovis don't get a random mac address on boot.
Additionally, program the LAN WAKE GPIO properly as per the Ovis
schematics dated July'23.
BUG=b:293905992
TEST=Verified on google/ovis that able to get the fixed MAC address across the power cycles.
Change-Id: I699e52e25f851de325f96ef885e04d15ca64badd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76872
Reviewed-by: Jakub Czapiga <jacz@semihalf.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-08-02 18:15:41 +00:00
eb988dfcba
acpi/acpi.c: Move setting FADT SCI INT to arch specific code
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: Ic1533cb520a057b29fc8f926db38338cd3401b18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76295
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
2023-08-02 17:11:32 +00:00
cd46e5f63a
acpi/acpi.c: Add and use acpi_arch_fill_madt()
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I4e5032fd02af7e8e9ffd2e20aa214a8392ab6335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76070
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2023-08-02 17:11:06 +00:00
51d94c7d73
acpi/acpi.h: Add MADT GIC structures
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I9e6544c956cb3d516d2e5900357af9ae8976cc8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76131
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2023-08-02 17:10:16 +00:00
1cdeaea8d9
acpi.c: Add FACS and DSDT to debug hex printing
...
TESTED acpixtract -a is able to extract all the dumped tables including
FACS and DSDT.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I7fad86ead3b43b6819a2da030a72322b7e259376
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
2023-08-02 17:07:38 +00:00
ba2e354af4
arch/arm64: Hook up FADT
...
Arm needs very little of FADT. Just a HW reduced model bit and low power
idle bit set.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I197975f91cd47e418c8583cb0e7b7ea2330363b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76180
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-02 15:53:26 +00:00
8473e8fd5f
acpi.c: Fill in >4G FADT entries correctly
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I84ab0068e8409a5e525ddc781347087680d80640
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2023-08-02 15:53:02 +00:00
28857ce317
mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
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Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for Samsung K4U6E3S4AB-MGCL.
BUG=b:293240969
TEST=emerge-dedede coreboot
Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-08-02 15:11:47 +00:00
d97d860f23
mb/google/nissa/var/craaskov: Configure GPIOs according to schematics
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Configure GPIOs based on schematics and confirm with EE.
BUG=b:290248526
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Derek Huang <derekhuang@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com >
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
2023-08-02 14:40:03 +00:00
7333901701
mb/google/nissa/var/joxer: support DPTF oem_variables
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1. Joxer uses dptf.dv to distinguish 6W/15W by setting OEM variable.
2. Update passive policy and critical policy.
BUG=b:285477026, b:293540179
TEST=emerge-nissa coreboot and check the OEM variable.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com >
Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-by: Derek Huang <derekhuang@google.com >
Reviewed-by: Ivan Chen <yulunchen@google.com >
2023-08-02 14:25:16 +00:00
6af7261b2b
acpi.c: Guard FACS generation
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It's not expected that non-x86 arch implement x86 style sleep states and
resume.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76178
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-02 06:31:35 +00:00
5afd9b4e87
3rdparty/libgfxinit: Uprev to avoid new GCC 13 warning
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This pulls just one commit:
* commit a4be8a21b0e2 (Avoid warning '"Pos32" is already use-visible')
Change-Id: I908d5f2b98e2251a09c587d82b3e7fab55b338a2
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76868
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-02 04:00:30 +00:00
d5ac7b3c85
3rdparty/libhwbase: Uprev to avoid new GCC 13 warning
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This pulls just one commit:
* commit 584629b9f477 (Avoid warning '"Pos64" is already use-visible')
Change-Id: I816f915d991d3d436d0468ca411037b1dc6d0e56
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76867
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
2023-08-02 03:59:27 +00:00
fdb4503e62
Revert "util/amdfwtool: Add some PSP entries to both levels"
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This reverts commit 91f5da4776matt.devillier@amd.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76718
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-08-01 20:28:53 +00:00
37cae5cea2
soc/amd/mendocino: select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR
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Select this Kconfig to ensure the PSP_ADD_MSR is properly programmed
across all cores.
This resolves a Windows BSOD "CRYPTO_LIBRARY_INTERNAL_ERROR."
BUG=b:293571109
BRANCH=skyrim
TEST=build/boot google/skyrim, use rdmsr to verify MSR value identical
across all cores.
Change-Id: I67391b49496d767912f5d81c1758a52a70fca6f6
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76809
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-01 17:57:18 +00:00
43a9ffb590
nb/sandybridge: Remove redundant include of "ddr3.c"
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It is already selected here device/dram/Makefile.inc
Change-Id: I32a1ecc4e0f90725f9356158ce2978502b590d5c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76390
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-01 17:00:42 +00:00
60a8a7de5a
drivers/usb/ehci.h: Use C99 flexible arrays
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Ideed4b333632df5068b88dde6f89d3831e3046d1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
2023-08-01 13:38:48 +00:00
295f6bf8d4
linux_trampoline: Handle coreboot framebuffer
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Translate the coreboot framebuffer info from coreboot tables to
the Linux zero page.
Tested in QEMU/Q35 with a kernel w/ efifb enabled.
Change-Id: I2447b2366df8dd8ffe741c943de544d8b4d02dff
Signed-off-by: Nico Huber <nico.h@gmx.de >
Co-authored-by: Bill XIE <persmule@hardenedlinux.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76431
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com >
Reviewed-by: Samuel Holland <samuel@sholland.org >
Reviewed-by: Bill XIE <persmule@hardenedlinux.org >
2023-08-01 13:37:19 +00:00
d1b8589583
drivers/mipi: sta_ili9882t: Change TReset-CMD from 1.1 ms to 20 ms
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In the datasheet of ILI9882T [1] section 3.11 Power On/Off Sequence,
the TReset-CMD (Reset to First Command in Display Sleep In Mode) should
be larger than 10ms, but it's 1.1ms now. This may cause abnormal
display as some commands may be lost during power on. Fix this and
leave some margins by increasing TReset-CMD to 20ms. Also, to align
with the kernel driver structure starry_ili9882t_init_cmd, add 20ms
delay at the end of command.
[1] ILI9882T_Datasheet_20220428.pdf
BUG=b:293380212
TEST=Boot and display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com >
Change-Id: Ifdcaf0e34753fc906817c763f1c8e7389448d1dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76766
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Yidi Lin <yidilin@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2023-08-01 13:35:19 +00:00
40c645b137
lib/gcov-io.h: Use C99 flexible arrays
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Iad9cbe16a2d1881d74edcc702be843168df8a4ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
2023-08-01 13:34:27 +00:00
3dc221fac3
commonlib/tpm_log_serialized.h: Use C99 flexible arrays
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I16ac584781214350355e0625f8a2eca39a37cf85
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
2023-08-01 12:56:19 +00:00
39aee649da
vendorcode/google: Use C99 flexible arrays
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Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I81ae8acb0365af102e513b3d7cfa1a824636eb06
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76812
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-08-01 12:56:06 +00:00
