Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS.
Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs.
Use BIOS_ERR of printk() for FSP errors.
BUG=N/A
TEST=Check console output on Facebook FBG1701.
Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Use of romstage_ram_stack_bottom() was invalid, it
potentially uses a different ROMSTAGE_RAM_STACK_SIZE
from the postcar_frame_init() call.
If alignment evaluated to 1 MiB, that WB MTRR may not
have covered all of CBMEM range, having some impact
on boot speeds.
There is no need to accurately describe write-back
MTRR ranges for postcar.
Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set
to ENV_RAMSTAGE.
This approach will help to add future optimization (rampayload) in
coreboot flow if required.
Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
* Add chips ops for IPMI KCS.
* Get IPMI version over KCS.
* Generates ACPI SPMI table for IPMI KCS.
* Generates SMBIOS type 38 for IPMI KCS.
* Generates ACPI SPMI device for IPMI KCS on LPC device.
* Add documentation
To use this driver on BMC that support KCS on I/O:
1. Add an entry to the devicetree.cb:
chip drivers/ipmi
device pnp ca2.0 on end # IPMI KCS
end
2. Select IPMI_KCS in Kconfig.
3. (Optional) enable LPC I/O decode for the given address.
Tested on Wedge100s.
Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The upstream vpd_decode.c has been revised to prevent overrun of decoded
contents.
BUG=chromium:967209
TEST=select VPD config on kukui; make; boots on at least kukui boards.
Change-Id: I1a50670a66b7b174d2a432c29d90152b86c32982
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Coverity believes there is a path where StdHeader is possibly
null. This *should* be incorrect, since the header is actually
initialized through the module dispatch framework, though Coverity
can't see it due to the extensive type-punning. However, the control
flow is so dizzingly complicated that I'm not even completely sure,
so adding an extra assert to be careful won't hurt anyway.
Change-Id: If3d7c5d5c5bba846e7453b3dbc824e2208d749fb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1379932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Set abort command define
* Set debug level to SPEW
* Support zero length data packet in ipmi_kcs_send_message
That's required for commands like GET_DEVICE_ID, which have no
additional data to send.
* Read reply even if given no receive buffer
* Prevent buffer overflow in read reply processing
Tested on Wedge100s.
Change-Id: Iefddd88a744c3b96751d3fe8c2951ca2115548ce
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33488
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds support to read SPI flash in Dual SPI mode, where both
MISO and MOSI lines are used for output mode (specifically Fast Read
Dual Output (0x3b) where the command is still sent normally, not Fast
Read Dual I/O (0xbb) whose additional benefit should be extremely
marginal for our use cases but which would be more complicated to
implement). This feature needs to be supported by both the flash chip
and the controller, so we add a new dual_spi flag (and a new flags field
to hold it) to the spi_flash structure and a new optional xfer_dual()
function pointer to the spi_ctrlr structure. When both are provided,
Dual SPI mode is used automatically, otherwise things work as before.
This patch only adds the dual_spi flag exemplary to all Winbond and
Gigadevice chips, other vendors need to be added as needed.
Change-Id: Ic6808224c99af32b6c5c43054135c8f4c03c1feb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All SPI flash chip drivers currently in coreboot use the generic read
functions (spi_flash_cmd_read_fast()/_slow()) as their read callback.
The only use case for specialized read callbacks we have left is with
specialized flash controllers like Intel fast_spi (which sort of
impersonate the flash chip driver by implementing their own probe
function).
This patch unifies the behavior for all normal flash drivers by making
the read callback optional and letting them all fall back to a default
read implementation that handles normal fast/slow reading. Most of the
drivers used to install the respective callback after checking
CONFIG_SPI_FLASH_NO_FAST_READ, but some hardcoded either slow or fast
writes. I have found no indications for why this is and spot-checked
datasheets for affected vendors to make sure they all support both
commands, so I assume this is just some old inaccuracy rather than
important differences that need preserving. (Please yell if you
disagree.)
Also take the opportunity to refactor some of the common spi_flash.c
code a bit because I felt there are too many nested functions that don't
really do enough on their own, and centralizing stuff a bit should make
it easier to follow the code flow. (Some of this is in preparation for
the next patch.)
Change-Id: I2096a3ce619767b41b1b0c0c2b8e95b2bd90a419
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch changes the Gigadevice SPI flash driver to adopt the same
structure packing improvements for the hardcoded parameters of
individual chips that was implemented for Winbond last year. This cuts
the size of the hardcoded info nearly in half and should save us a few
hundred bytes in every stage.
Change-Id: I9910dcb9b649f51b317f3f8fcba49e5e893f67d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get
in the way (just adding one line per stage, essentially) and should have
no notable overhead. Let's enable it by default for the BIOS_DEBUG log
level rather than having to recompile to get it.
Also fix an issue with building this code on MIPS due to lack of 64-bit
division primitives. (This means MIPS and arm32 board may display
incorrect results when reading more than 4MB in a single transfer, which
sounds very unlikely.)
Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix
disabling iGPU in 'Dual Graphics' on Lenovo T430.
* Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select
DRIVERS_LENOVO_HYBRID_GRAPHICS.
Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The code in cpu/intel/car/romstage.c Does most of the things like
setting up timestamps, stack guards, entering postcar.
A functional difference is that the FSP header is searched for twice
instead of passed from the CAR entry to the C code. When using
C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special
linker symbol kept across multiple stages is needed, which is likely
not worth the speedup).
Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Instead of dereferencing a null pointer, print a nice message and exit
cleanly if the FSP isn't found in the CBFS.
Change-Id: I761e7febc7cec5bd2ef3af214bc51777ee5c313d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401467, 1401717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33049
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is possible that acpi_device_scope() and acpi_device_name() can
return NULL to indicate an error, so add error handling to check their
return values.
Change-Id: I4c7ab0c592845d9d5f142e078fc2b505a99ecd12
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1362592
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This list is incorrect and not up to date. The FSP1.1 romstage
bootflow is unnecessarily clumsy and instead of trying to update this
comment effort is better spend making the bootflow more streamlined.
Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
