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Author SHA1 Message Date
Angel Pons
4dadeb3f22 mb/google/auron/var/lulu: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Lulu remains identical.

Change-Id: I0f0a584b3354971ee8d478fd17825e498ff3e423
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50072
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:50:56 +00:00
Angel Pons
7ad729c136 mb/google/auron/var/gandof: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Gandof remains identical.

Change-Id: I168fcad7088706ca5b21f5fbf6790b13054499e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50071
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:50:36 +00:00
Angel Pons
d1ff7e43b5 mb/google/auron/var/buddy: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Buddy remains identical.

Change-Id: I6e6256a9cc88c9d0743150bfdf12b1b482fe157d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50070
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:50:21 +00:00
Angel Pons
6259aeb86e mb/google/auron/var/auron_yuna: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Auron Yuna remains identical.

Change-Id: I17e6bf20114f43da2897ec320ca26d8c6f6a4b09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50069
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:49:42 +00:00
Angel Pons
bb95f24115 mb/google/auron/var/auron_paine: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Auron Paine remains identical.

Change-Id: I00b9184fe6f002c3e089c9fbc815862d60e7694f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50068
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:49:17 +00:00
Angel Pons
2d11f71220 mb/intel/wtm2: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Intel WTM2 remains identical.

Change-Id: I422421cc3c336a7a1aceaff7b37ab7c82f64a03f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50067
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:48:46 +00:00
Angel Pons
2126aecb32 mb/purism/librem_bdw: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I573cd439e8284d84036e71615944f7a195155593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50066
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:48:32 +00:00
Tim Wawrzynczak
d4749184c2 mb/google/brya: Add EC I/O decode windows 
BUG=b:180013349
TEST=console shows successful EC <-> SoC communications

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-02-15 08:25:47 +00:00
Tim Wawrzynczak
ad21d6bfca mb/google/brya: Enable cr50 support 
Add Kconfig options and devicetree entries for cr50 TPM.

BUG=b:180017621
TEST=verify (via console) successful cr50 communications in
verstage and payload (depthcharge).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-02-15 08:25:36 +00:00
Mathew King
91a2cd4770 mb/google/guybrush: Configure non-native function GPIOs 
Second pass GPIO configuration to enable the non-native function
GPIOs based on the guybrush Proto 0 reference schematic 0210.

BUG=b:177909472
TEST=builds

Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-02-15 08:22:53 +00:00
Raul E Rangel
f41ca1ed76 soc/amd/cezanne: Add uart.c to smm so we can support DEBUG_SMI 
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife43352db564654ed538383a157431ee10856518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-15 08:22:27 +00:00
Angel Pons
ec38570ead nb/intel/sandybridge: Correct description of QCLK 
QCLK means "quadrature clock", and is equivalent to one half of a full
clock cycle (tCK). Fix the comment. The `QCLK_PI` value is still valid.

Change-Id: I7089fc32381addc280a71761a377075f107b5c62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49363
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:21:33 +00:00
Patrick Rudolph
fc36e9fb0e soc/intel/*: Move prmrr_core_configure 
Move prmrr_core_configure before clearing MCEs.

This is required for the following patch in order to update microcode
after PRMRR has been configured, but before MCEs have been cleared.

According to Document 565432 this should be no issue in regards to
SGX activation.

Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-15 08:20:19 +00:00
Angel Pons
aacbd66a85 sb/intel/lynxpoint: Clean up lp_gpio.h 
Move `mainboard_gpio_map` declaration inside header and reorder some
function declarations. This is to align the header with Broadwell.

Change-Id: I436d7fdabf8d574e5dd2787fb6097f384cc8e453
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50065
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:19:14 +00:00
Angel Pons
f76822a75c soc/intel/broadwell/pch: Rename GPIO identifiers 
Rename structs, types and functions to match Lynx Point's names.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:19:03 +00:00
Maxim Polyakov
19d4364ed6 intel/xeon_sp/util: Use get_stack_busno instead of get_cpubusnos 
This function is more convenient to get the value of a single bus number
than get_cpubusnos(). Now get_cpubusnos is not used anywhere, so remove
it.

Change-Id: I71c06c2d69344d97e48609e67a3966ed8c671152
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-15 08:18:07 +00:00
Mike Banon
f124939945 tint: update the patch version numbers according to a new tint version 
Rebase the libpayload_tint.patch to update its internal version
numbers from 0.04+nmu1 to 0.05.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I91f780f80026147c3c35330625a4106c65a1ddf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50468
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:17:51 +00:00
Felix Held
b03dc9c12b soc/amd/picasso: always include PSP secure OS in amdfw 
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-14 21:58:10 +00:00
Angel Pons
6ab87664b7 arch/x86: Drop cstates pointer from CPU drivers 
Nothing uses this pointer anymore.

Change-Id: Id2dee8f4cb243114d6f7f7485402acb9b73b7900
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49808
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:57:13 +00:00
Angel Pons
e49dec45c8 cpu/intel/haswell: Constify ACPI c-state arrays 
Change-Id: I5538d8279392238e59aba99ade4b5fe13f250ca8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49805
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:57:00 +00:00
Angel Pons
618b9ade15 cpu/intel/haswell: Drop c-state table indirection 
Accessing it directly allows proper bounds-checking.

Change-Id: Ifb539051e4a91ddcdb5ffec4850dc2fb30482aea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49804
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:54:55 +00:00
Angel Pons
85790d028f cpu/intel/model_206ax: Drop c-state table indirection 
Accessing it directly allows proper bounds-checking.

Change-Id: I2582a7edf5fba28febe570bddccacb85a3269684
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:54:48 +00:00
Angel Pons
d8b9e562d0 cpu/intel/model_206ax: Replace generate_cstate_entries 
Leverage the existing `acpigen_write_CST_package` function.

Yes, bad devicetree values can trigger undefined behavior. The old code
already had this issue, and will be addressed in subsequent commits.

Change-Id: Icec5431987d91242930efcea0c8ea4e3df3182fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49093
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:54:39 +00:00
Felix Held
ea32c52a0e soc/amd/cezanne: add partial data fabric setup 
I'm not 100% sure yet if this code will be common for all AMD SoCs, so
I'll add a copy for Cezanne for now. This part of the code should
probably be reworked after the initial bringup of Cezanne anyway.

DF MMIO register configuration at the beginning of
data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       a3     fc00     febf
  1       a3  1000000 fffcffff
  2       a3     d000     f7ff
  3       a0        0        0
  4       a3     fed0     fed0
  5       a0        0        0
  6       a0        0        0
  7       a0        0        0

DF MMIO register configuration at the end of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       a3     fc00     febf
  1       a3  1000000 fffcffff
  2       a3     d000     f7ff
  3     10a3     fed0     fedf
  4       a0        0        0
  5       a0        0        0
  6       a0        0        0
  7       a0        0        0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:48:23 +00:00
Felix Held
eb89ca67ef soc/amd/cezanne/include/iomap: add HPET base address 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72559147a3f86f0cb843b74af9b148d23229ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50623
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:48:03 +00:00
Felix Held
906f9be383 soc/amd/common/block/data_fabric: add data_fabric_print_mmio_conf 
Output on Picasso at the beginning of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       93     fc00     febf
  1       93  1000000 ffffffff
  2       93     d000     f7ff
  3       90        0        0
  4       93     fed0     fed0
  5       90        0        0
  6       90        0        0
  7       90        0        0

Output on Picasso at the end of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       93     fc00     febf
  1       93  1000000 ffffffff
  2       93     d000     f7ff
  3     1093     fed0     fedf
  4       90        0        0
  5       90        0        0
  6       90        0        0
  7       90        0        0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I74617dfc6099489f3c81d0e385b502f1bbecea78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50640
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:46:23 +00:00
Kyösti Mälkki
05af850b28 sb/amd/cimx/sb800: Move common OSFL method in ASL 
We deal with mb/lippert/frontrunner-af later since it currently
does not include <cimx/sb800/acpi/fch.asl>.

Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:36:48 +00:00
Kyösti Mälkki
29b030dfcf AGESA,binaryPI boards: Drop OSV in ASL 
Not referenced anywhere in ASL.

Change-Id: I52ac4722e48e1cc377386316dc034fb45a98181a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50471
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:36:14 +00:00
Kyösti Mälkki
d591a5a328 ACPI: Move common _PIC method 
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-14 21:35:47 +00:00
Kyösti Mälkki
fa6a85c850 sb,soc/amd: Drop empty CIRQ call from _PIC 
Change-Id: Iaa51e0530a3f72456d3d4e7a0c55b768ba63e322
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49904
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:35:11 +00:00
Kyösti Mälkki
3942a902cd sb/amd/cimx/sb800: Drop CIRQ method from _PIC 
Change-Id: Ie4aad7b6580100377c12f128905f7f409bdb5295
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50590
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:34:22 +00:00
Kyösti Mälkki
b57373b058 util/cbfstool: Fix build in 32-bit userspace 
Fix regression from commit 0dcc0662f3 util/cbfstool: Introduce
concept of mmap_window.

Use of region_end() wraps around at 4 GiB, if utility is run in
32bit userspace. The build completes with an invalid coreboot.rom,
while one can find error message in stdout or make.log:

E: Host address(ffc002e4) not in any mmap window!

Change-Id: Ib9b6b60c7b5031122901aabad7b3aa8d59f1bc68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-14 20:59:37 +00:00
Felix Held
985f3e05e3 soc/amd/picasso/data_fabric: factor out common MMIO register defines 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I663a73308d33f48c6b945007f3eaac84d4712f59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50639
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 20:53:47 +00:00
Felix Held
602f93ed52 soc/amd/picasso/data_fabric: move more helper functions to common code 
The number of data fabric MMIO registers is SoC-specific, so we need to
keep that in the SoC code. This also removes a redundant pair of
brackets and moves a loop counter declaration into the head of the loop.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 20:53:22 +00:00
Felix Held
0a1491366b soc/amd/picasso/data_fabric: use common access functions 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8cda860ca0ff81d7703c3277aeec629d89eab45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50622
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 20:53:08 +00:00
Felix Held
789f6f7c35 soc/amd/common/block/data_fabric: add data_fabric_broadcast_read/write32 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81e7ff293865ef22ed74606e1e79f67a460de4a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50621
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 20:52:53 +00:00
Felix Held
45df9c1b91 soc/amd/common/block/data_fabric: add data_fabric_write32 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c1ae03e9aec1dec45333e697060308cb6cbda4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50620
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 20:52:38 +00:00
Felix Held
dba3fe7ad1 soc/amd/picasso: move data_fabric_read32 to common code 
The exact same mechanism is used on Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 20:52:03 +00:00
Kyösti Mälkki
6962b6ecd3 sb,soc/amd: Move _PIC method to global scope 
Fix regression with commit aa969e887a ACPI: Move PICM declaration.

While mentioned in the commit message there already, the default
value for AMD boards changed from IOAPIC mode to PIC mode.

ACPI 6.3 spec has this text regarding _PIC method:

  If the platform CPU architecture supports PIC mode and the method
  is never called, the platform runtime firmware must assume PIC mode.

If MADT has IOAPIC entries, OS will want to change to APIC model. But
the method _PIC was not in the global scope so it could not be called
and therefore _PRT continued to report PIC model interrupt routing.

Already fixed for soc/amd/picasso in commit 839f668.

Change-Id: I7f3bb0d45946cec315694de1d540fea4d828348e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2021-02-14 19:21:03 +00:00
Felix Held
aed4aca3fc soc/amd/cezanne/chipset.cb: add SMBus and data fabric PCI devices 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica9b4adb1ec2b3663ce2d623cfe7b6539cd9c71b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50631
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 19:09:22 +00:00
Felix Held
65418cc8b5 soc/amd/cezanne: move CPU cluster to chipset device tree 
This will be common for all boards, so move it to the chipset device
tree.

TEST=CPU cluster and LAPIC still show up in console logs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 18:22:49 +00:00
Raul E Rangel
ffdf840dbb mb/amd/majolica/mainboard: Set ACPI IRQ 
We now pass the ACPI SCI IRQ to the OS, so make sure the board routes it
correctly.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1b4d5e0bfb1d9df9ac8a8c41cdf466a67f2673d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2021-02-14 18:15:56 +00:00
Raul E Rangel
12c6a58857 soc/amd/cezanne: Fill FADT and MADT 
The MADT doesn't populate the IO-APICs yet since we need FSP to
configure those.

The FADT differs from picasso in the following ways:
* The duty_offset is supposed to be 0
* Don't clear x_firmware_ctl_l
* Make the extended addresses use MMIO

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-14 18:13:56 +00:00
Raul E Rangel
35dc4b0ede soc/amd/cezanne: Enable uCode update 
TEST=Boot majolica and see microcode update
CBFS: Found 'cpu_microcode_blob.bin' @0x6900 size 0x15c0 in mcache @0xcf7fe9d8
microcode: patch id to apply = 0x0a50000b
microcode: being updated to patch id = 0x0a50000b succeeded

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If50b1d8b3ebf4b3e6f8a9dd3ab96073e0cb92424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-14 18:05:26 +00:00
Raul E Rangel
394c6b0922 soc/amd: Move update_microcode.c to common/block/cpu 
We also want to support uCode loading on cezanne.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-14 18:05:17 +00:00
Elyes HAOUAS
844775059d superio/smsc/sch5545: Add missing <types.h> 
Add needed but missing <types.h>.

Change-Id: I16c6a86e8c8863a8e16a63a379484c2b47d5185e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-13 22:06:28 +00:00
Raul E Rangel
f5552cef97 include/acpi/acpi.h: Add ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS 
This is a magic value that means all processors.
See Table 5-52 Local APIC NMI Structure in ACPI Spec 6.3.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic2fc060fda21bec44258bcae62ddb230be542759
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-13 21:54:54 +00:00
Felix Held
86024954df soc/amd/cezanne: select ACPI support and make the compiler happy 
Follow-up patches will add more functionality.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-13 21:39:16 +00:00
Raul E Rangel
07acbfc6a5 soc/amd/common/acpi/gpio_bank_lib.asl: Add missing header 
This file references ACPIMMIO_GPIO0_BASE.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic65a1f8759d10e7d78e30cfc82895e5af8cd83a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50571
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-13 21:38:53 +00:00
Raul E Rangel
984ecf9e74 mb/google/guybrush: Add plain dsdt 
Needed to enable ACPI support for cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-13 21:38:30 +00:00