It is useful to know if MCU have been applied successfully.
On the start of MP init lines similar to:
"AP: slot 1 apic_id 1, MCU rev: 0x0700001d" will be printed.
The example is taken from the log of an ocp/deltalake.
Change-Id: Ia0a6428b41d07f87943f3aa7736b8cb457fdd15a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49840
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With top-aligned bootblock this is no longer globally needed.
The default maximum is now a generous 256 KiB with couple
platforms having lower limits of 32 KiB and 64 KiB.
Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for
both the traditional and ULT variants of Broadwell, because the CPU
driver for Haswell already contains CPUIDs for both Broadwell types.
Without this patch, Broadwell CPUs would hang when trying to print the
first console log message, but only if flashconsole was not enabled.
This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell
CPUIDs and microcode) and went unnoticed until now because the tests
were done with flashconsole enabled, which somehow boots properly even
though the console time tracking would not work (depends on TSC).
Tested on out-of-tree Acer E5-573, fixes booting without flashconsole.
Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the mainboards have the magic SpeedStep device, so the C-state
generation function bails out without doing anything. Moreover, this
code is broken and was copied from Sandy Bridge. Thus, drop it.
Change-Id: I580157ee33c599af5fc48b06eeb39cb32c9831ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Broadwell code unconditionally enables timed MWAIT, but not all Haswell
steppings support it. In preparation for merging Haswell and Broadwell,
also enable timed MWAIT on Haswell code, but only if it is supported.
Change-Id: I1d11d62f1801d65ae4d5623994fd55fd35e8f34a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46916
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `mobile` suffix is misleading, since desktop CPUs share the same
CPUIDs. Remove unused stepping IDs and add the full CPUIDs instead.
Finally, add Broadwell CPUIDs in preparation for merging CPU code.
Note that steppings for Haswell in various comments are incorrect.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I19e56b8826b1514550ae95e6363b0df2d08e3cb7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Backport Broadwell's s0ix support to Haswell in preparation to unify
both platforms' CPU code. Note that only ULT variants support s0ix.
This option is currently unused, but will be put to use in subsequent
commits, when switching Broadwell mainboards to use Haswell's CPU code.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I91c6f937c09c9254a6f698f3a6fb6366364e3b2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46924
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase DCACHE_RAM_SIZE to 32kB and remove "NO_CBFS_MCACHE".
It’s quite safe to increase DCACHE_RAM_SIZE. All LGA775 targets
should have at least 256K L2 cache. That is plenty for XIP RO cache of
bootblock + romstage and a 32K CAR.
Change-Id: I393b2727bd90a990c3108a4dbead62b17d7fc531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Writing 0 to MSR IA32_BIOS_SIGN_ID before fetching this MSRs content
is required. This is how things are done in
cpu/intel/microcode/microcode.c.
The "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
also recommends this: "It is recommended that this field be preloaded
with 0 prior to executing CPUID" (this field being %edx).
Change-Id: I24a87aff9a699ed8ab2598007c8b8562d0555ac5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change affects Intel CPUs only. As most platforms are doing
uCode update using FIT, they aren't affected by this code either.
Update microcode in MP-init using a single spinlock when running on
a Hyper-Threading enabled CPU on pre FIT platforms.
This will slow down the MP-init boot flow.
Intel SDM and various BWGs specify to use a semaphore to update
microcode on one thread per core on Hyper-Threading enabled CPUs.
Due to this complex code would be necessary to determine the core #ID,
initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2.
Instead use the existing global spinlock already present in MPinit code.
Assuming that only pre-FIT platforms with Hyper-Threading enabled and at
most 8 threads will ever run into this condition, the boot delay is
negligible.
This change is a counterproposal to the previous published patch series
being much more unsophisticated.
Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.
Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).
While at it, also add the addition to the PHONY target so we don't
forget it.
BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.
Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 542307b815 (broadwell: Add small delay before Flex Ratio reboot)
introduced a workaround for Broadwell. Implement it on Haswell as well.
Since this is only necessary when a TPM is present on a system, only do
the delay (which is not that small, to be honest) on TPM-enabled builds.
Change-Id: Id8b58e9fa2a1c81989305f5b4b765b82c01e1596
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46941
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MSR only needs to be set when IO MWAIT redirection is to be enabled.
This was copied from Sandy Bridge, which already had this inconsistency.
Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46917
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To work around various bugs running KVM enabled, copy page tables to
DRAM in assembly before jumping to x86_64 mode.
Tested on QEMU using KVM, no more stange bugs happen:
Tested on host
- CPU Intel(R) Core(TM) i7-7700HQ
- Linux 5.9
- qemu 4.2.1
Used to crash on emulating MMX instructions and failed to translate
some addresses using the virtual MMU when running in long mode.
Tested on host
- CPU AMD EPYC 7401P 24-Core Processor
- Linux 5.4
- qemu 4.2.1
Used to crash on jumping to long mode.
Change-Id: Ic0bdd2bef7197edd2e7488a8efdeba7eb4ab0dd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
