sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
29,466 Commits 47 Branches 30 Tags
95778bf7ea0a45e429d8822857947b6994ea0c7f
Commit Graph

29466 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Elyes HAOUAS
adc3235eb7 cpu/amd/family_10h-family_15h: Fix 'if' condition identical branches 
Change-Id: I1c937a62388c38090ee2cc3228973cfb8361bac7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2019-06-21 08:35:01 +00:00
Elyes HAOUAS
283b438f5c soc/intel/common/block/pcr: Remove unneded 'else' 
'else' is not needed after a 'break' or 'return'.

Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33336
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-21 08:33:35 +00:00
Elyes HAOUAS
c166071beb mb/google/snappy: Remove unneeded 'else' 
'else' is not needed after a 'break' or 'return'.

Change-Id: I7b6c319a58b9f4f47de19336d18d00b73d3d3772
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-21 08:32:57 +00:00
Elyes HAOUAS
1ba0da17c8 ec/kontron/kempld/kempld_i2c.c: Remove unneeded 'else' 
'else' is not needed after a 'break' or 'return'.

Change-Id: I0843bebe48e4b91fc76c440ae33bbca838621de9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-21 08:32:32 +00:00
Elyes HAOUAS
b53427156c ec/google/chromeec/ec_lpc: Remove unneeded 'else' 
'else' is not needed after a 'break' or 'return'.

Change-Id: I98d0ab0d139186b312e8c1086c475ba6ef0b7d3b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-21 08:32:08 +00:00
Elyes HAOUAS
561e11d6f8 drivers/intel/fsp1_0/fastboot_cache: Remove unneeded 'else' 
'else' is not needed after a 'break' or 'return'.

Change-Id: I109f5aaa87afde61a36fff884305b43c1de2c680
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-21 08:31:46 +00:00
Elyes HAOUAS
77b3a91bba arch/x86/rdrand.c: Remove unneeded 'else' 
'else' is not needed after a 'break' or 'return'.

Change-Id: Ib7bdefb0027a35de42f6a665b98f9e5a2791061f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-21 08:31:19 +00:00
Jacob Garber
698d83a7c8 lib: Prevent memory leak on error path 
Free the tree before returning to prevent a leak.

Change-Id: I1132c0e7404eec1af3adc19a83257f28563f8a58
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2019-06-21 08:31:02 +00:00
Jacob Garber
176670e31a drivers/amd/agesa: Assert that StdHeader is non-null 
Coverity believes there is a path where StdHeader is possibly
null. This *should* be incorrect, since the header is actually
initialized through the module dispatch framework, though Coverity
can't see it due to the extensive type-punning. However, the control
flow is so dizzingly complicated that I'm not even completely sure,
so adding an extra assert to be careful won't hurt anyway.

Change-Id: If3d7c5d5c5bba846e7453b3dbc824e2208d749fb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1379932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-06-21 08:30:24 +00:00
Jacob Garber
31755adc5a nb/amd/amdmct/mct: Remove duplicate if condition 
The case when Speed == 5 is already dealt with on line 111.

Change-Id: Icc41c00fb333a51001568f588c17f7b6c6a3a923
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229626
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-21 08:30:00 +00:00
Jacob Garber
19cbe03534 nb/amd/amdmct/mct_ddr3: Remove duplicate conditional 
This check is already performed at the beginning of
dct_ddr_voltage_index().

Change-Id: Ia73025333c152f14249afb16d05f66791e69e7cb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347322, 1347323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-21 08:29:45 +00:00
Jacob Garber
86d8c4279d nb/amd/amdmct/mct_ddr3: Remove duplicate code 
This conditional is exactly the same as the one right below it, except
the operations are reorganized slightly.

Change-Id: I00c19a467d23a0736bc2a33b516f97080039e634
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-21 08:28:53 +00:00
Joel Kitching
532e0c74e1 vboot: relocate code to log and clear recovery mode switch 
Logging and clearing the recovery mode switch doesn't have
anything to do with vboot_handoff.  Move it to the main verstage
logic file.

BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I2e74f3893463e43fe5fad4a8df8036560f34e0db
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2019-06-21 00:52:35 +00:00
Joel Kitching
b6bcb6cc8f vboot: remove functions which read vboot_handoff.out_flags 
These functions are no longer used and may be removed:
* vboot_handoff_check_recovery_flag
* vboot_get_handoff_flag

BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ie05652ef1288eef74bd2e7e8bea79fd29d523859
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33533
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-21 00:50:59 +00:00
Joel Kitching
a06cd6c29e vboot: remove vboot_handoff_get_recovery_reason 
Two functions retrieve vboot recovery_reason:
* vboot_handoff_get_recovery_reason
* vboot_get_recovery_reason_shared_data

Previously, when CBMEM comes online, a vboot_handoff data
structure is created, and depending on the architecture,
coreboot may eventually lose access to vboot_working_data.

After implementing vboot_working_data CBMEM migration,
vboot_working_data is always guaranteed to be accessible.

vboot_get_recovery_reason_shared_data is corrected to also
allow accessing vboot_working_data in ramstage and postcar.

Now, vboot_handoff_get_recovery reason returning a valid recovery
reason implies that vboot_get_recovery_reason_shared_data should
*also* return a valid recovery reason.  Thus we may remove the
former.

BUG=b:124141368, b:124192753
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Iac216dc968dd155d9d4f8bd0f2dfd5034762f9a0
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2019-06-21 00:50:48 +00:00
Hsin-Hsiung Wang
c10af299ae mediatek/mt8183: Calibrate vsim2 to 2.7 V 
The default voltage of vsim2 is set to 2.76V for sim card usage.
In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage.
However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V.
So we set it to 2.7V with modifying calibration value.

BUG=b:126139364
BRANCH=none
TEST=measure vsim2 voltage with multimeter

Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2019-06-21 00:06:02 +00:00
Jeremy Soller
87e186e7a8 Update gpe config 2019-06-20 15:58:29 -06:00
Jeremy Soller
d1e6a842c7 Fix gpio miscfg register values 2019-06-20 15:58:20 -06:00
Jeremy Soller
1d39c09349 Add more EC RAM items 2019-06-20 14:51:32 -06:00
Jeremy Soller
fcba28382a Fix order of outb 2019-06-20 14:51:16 -06:00
Jeremy Soller
2e9bae8216 Fix PMC GPP mappings 2019-06-20 14:51:05 -06:00
Jeremy Soller
0bcf238f2c Update gpio's after fixing coreboot-collector 2019-06-20 13:57:30 -06:00
Frans Hendriks
863853cd2d soc/intel/braswell/smbus.c: Add support for i2c mode block write 
Intel Braswell supports i2c block write using SMBus controller.

smbus_i2c_block_write() is added to configure SMBus controller in i2c
mode before calling do_i2c_block_write().

Add smbus.c to ramstage.

BUG=N/A
TEST=Verify LCD display is working on Facebook FBG-1701

Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-06-20 15:41:37 +00:00
Frans Hendriks
e48be35bca southbridge/intel/common/smbus: Add do_i2c_block_write() 
Intel Braswell supports i2c block writes using SMBus controller.
This support is missing in actual smbus routines.

Add do_i2c_block_write() which is a based on do_smbus_block_write() but
also write first byte to SMBHSTDAT1.
The caller needs to configure the SMBus controller in i2c mode.

In i2c mode SMBus controller will send the next sequence:
SMBXINTADD, SMBHSTDAT1, SMBBLKDAT .. SMBBLKDAT

To ensure the the command is send over the bus the SMBHSTCMD register must
be written also

BUG=N/A
TEST=Config eDP for LCD display on Facebook FBG-1701

Change-Id: I40f8c0f5257a62398189f36892b8159052481693
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-06-20 15:25:51 +00:00
Aamir Bohra
b09de70eda mb/google/hatch: Remove unused USB2 port5 from baseboard devicetree 
Hatch newer board revision do not use USB port5 for discrete BT.
Hence remove the port configuration and UBS2 P5 asl entry. The older
board version would continue to use USB2 P5 hence moved the entry to
overridetree.cb

Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2019-06-20 08:48:54 +00:00
sridhar
685b377e7e mb/intel/whl_rvp: Configure FSP UPDs of DDI ports for whlrvp 
This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.

BUG=none
TEST=Tested that eDP & DP works on WHLRVP

Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-19 19:35:56 +00:00
Elyes HAOUAS
ba5f318736 sb/nvidia/ck804/fadt.c: Remove unused LONG_FADT 
LONG_FADT is not used at all. So remove it and use sizeof(acpi_fadt_t) for
header length.

Change-Id: I433d1b2e0f3b9505d7c52eb14f1a476fbe52a284
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
 2019-06-19 19:35:05 +00:00
Elyes HAOUAS
0c5666828d {mb,sb}: Use get_acpi_table_revision(FADT) 
Change-Id: Id3d7f021a52e08906ae0a3f794756e397601fe96
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33428
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-19 19:34:10 +00:00
Arthur Heymans
f957201cf0 sb/intel/common/spi: Properly check if setting FRP succeeded 
Change-Id: Ib0b63c3b0342c62aeabb5c6e418eb9811fc6597d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-06-19 19:33:06 +00:00
Raul E Rangel
1264d64a74 grunt: Change Bayhub eMMC base clock to 200MHz 
The clock was previously set to 52MHz to workaround the fact that
depthcharge didn't support tuning.

Tuning has now been enabled in depthcharge:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553

BUG=b:122244718
TEST=Verified on grunt that it speeds up boot by 130ms

Change-Id: If847cea2a7848bcd175958db86e652d4f710201a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2019-06-19 19:29:35 +00:00
Marshall Dawson
ce2b2bad77 util/amdfwtool: Update for Family 17h 
Add arguments for additional PSP blobs needed with Family 17h support,
including the new AGESA binary loaders.

Create a new type of structure and entry for a BIOS directory table,
containing PMU code, microcode updates, as well as the BIOS initial
code.

Details on each of these items may be found in the AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors
(NDA only, #55758).

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2019-06-19 19:14:39 +00:00
Elyes HAOUAS
3f347a1379 lib/spd_bin.c: Remove unused include <arch/byteorder.h> 
Change-Id: Ifb8171e559c5c8081597291ffefabc676c7fa5e1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-19 12:30:04 +00:00
Elyes HAOUAS
b79a04c716 src/mainboard: Remove unused include <arch/byteorder.h> 
Change-Id: I3d638febddbd88cd4870795f96dd1bbf123c7ba3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33537
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-19 12:29:18 +00:00
Peter Lemenkov
22230687aa mb/lenovo/*/romstage: Remove unused include byteorder.h 
Change-Id: I3e500aafd26b7524a6782883b9a30f55b544102d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33511
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-19 12:28:24 +00:00
Peter Lemenkov
ca70593d0f mb/lenovo/z61t/romstage: Remove unused include 
This commit follows up on commit commit 89989cf6 with Change-Id:
I1f44ffeb54955ed660162a791c6281f292b1116a ("src: Drop unused include
<arch/acpi.h>").

Change-Id: I3dc12373b32b95d25ba7b302cbca5f927678315d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33365
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-19 12:27:14 +00:00
Peter Lemenkov
fab13583b5 mb/lenovo/t60/romstage: Remove unused include 
This commit follows up on commit 8b7a1614 with Change-Id:
I73c557d6ef009fb2cac35fdea500dee76f525330 ("src/mainboard: Remove
unneeded include <arch/io.h>").

Change-Id: I7f307bf5b6cdcfebe1a290ce344b962fcecc8781
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-06-19 12:26:41 +00:00
Peter Lemenkov
e625d07106 mb/lenovo/x201: Remove unneeded includes 
Tested: still builds fine.

Change-Id: I1ca4e42bd75a3e84afe8b30a60f02058b590416f
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-06-19 12:25:48 +00:00
Christian Walter
ac7eee4051 src/arch/x86/smbios: Change SMBIOS Version to 2.8 
Change the SMBIOS Version from 2.7 to 2.8. Necessary changes were
already pushed in https://review.coreboot.org/c/coreboot/+/33031

Change-Id: I237cdee7d43e814397b958e4cf941bf58949088d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-06-19 11:27:17 +00:00
Nico Huber
c6a584182e xcompile: Fix harmless typo 
As CFLAGS_GCC and CFLAGS_CLANG are still the same at this point, this
just removes some duplicate flags.

Change-Id: I532e5fa146891b70e4c1949c614b280055524593
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-06-19 11:27:09 +00:00
Patrick Rudolph
9d98e5ae0d acpi: Add SPMI table 
Add the SPMI table as defined in the IPMI spec v2:
https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Tested on Wedge100s.

Change-Id: Idff5134ce4c124f7e76acb0080da404b0c0dfffe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33487
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-19 11:26:54 +00:00
John Su
7752645041 mb/google/hatch/variants/hatch: Adjust all I2C CLK to meet spec 
After adjustment on Hatch
Touch Pad CLK: 383.4 KHz
Touch Screen CLK: 381.6 KHz
SAR Sensor CLK: 392.0 KHz
Audio codec CLK: 386.0 KHz

BUG=b:134911522
BRANCH=master
TEST=emerge-hatch coreboot chromeos-bootimage
     measure by scope with hatch.

Change-Id: Iee2b692c268381af267b70e92a577ac89ce41cbb
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2019-06-19 07:00:12 +00:00
Eric Lai
b90739d73d drivers/i2c/sx9310: Print I2C SAR device info 
Print I2C SAR device info so that it is available in cbmem logs.

BUG=none
BRANCH=none
TEST=Boot up and check cbmem -c can find the SAR I2C info

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia143932bb660ed2c2cea76310f11ede2b727adf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33432
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-18 21:15:23 +00:00
Jacob Garber
ce0c5334a0 sb/amd/cimx/sb900: Change logical negation to bitwise 
data &= !BIT0 will clear data, since !BIT0 evaluates to 0 (oops). We
only want to clear bit 0, not the whole thing, so use bitwise negation
instead.

Change-Id: I2179119e0d2d4aceaf4f8b499bf4c5baf4ef677f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1241812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2019-06-18 13:49:02 +00:00
Arthur Heymans
7407210a67 sb/intel/bd82x6x/lpc.c: Remove reinitializing the SPI driver 
This was done to update the global variable g_ichspi_lock but this is
now removed in favor of reading the lock bit during runtime instead of
keeping track of the state.

Change-Id: I8cb69a152b0e050d64d8979ee92de2d24136f8dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33390
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-06-18 13:39:09 +00:00
Arthur Heymans
816aaba399 sb/intel/spi: Check for the SPI lock bit during runtime 
The SPI swseq controller can be locked in other parts of the code, for
instance when it's locked down in the finalize section. The driver
has to be made aware of that. The simpler solution is to not keep
track of the state and simply read out the lock bit on each SPI
transfer.

Change-Id: Ifcd5121b89d6f80fc1c1368786982d0d9fa1bf61
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-18 13:11:41 +00:00
Arthur Heymans
21c5d43d72 sb/intel/common/spi.c: Add a pointer to the ich7 SPI registers 
Change-Id: I7509dc2124ee7057af075c7d0607ec615b930fa3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-18 13:11:19 +00:00
Arthur Heymans
a9c1a5f1f8 sb/common/intel/spi.c: Don't use typedefs for structs 
Change-Id: Id0ed621b5b4b5634d454811b1e1beeb27fc69ea8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-06-18 13:11:07 +00:00
Arthur Heymans
b0bbafe5ad soc/intel/skylake: Select microcode updates depending on discrete PCH 
Change-Id: I05e97484605306afc70c726187bda8091216c9cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-06-18 10:43:35 +00:00
Arthur Heymans
917420f7e8 Makefile.inc: Update 3rdparty/intel-microcode on USE_BLOBS 
Change-Id: I0caeff3ff5613a594a79441e849440ebdc9a9b87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-06-18 10:43:10 +00:00
zaolin
15110f12cb Add intel-microcode submodule repository 
Change-Id: Icc5ac0a8033e371ecf2b4b28ba45dab961e86b3f
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
 2019-06-18 10:42:17 +00:00