Contents of the EDID are passed by a reference to an array
of length 0x80, for which the macro 'PTN_EDID_LEN' has already
been around.
This patch makes use of this macro within the driver and mainboard
implementation utilizing it.
BUG=none
TEST=A successful build of mc_apl{1,4,5,7} and mc_ehl3 mainboards.
Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This is regarding issues observed on multiple Brya and Nissa
variant such as Skolas and Nivviks. Issue is that once coreboot
sets GPE_EN bit for the GPIO pin and locks it, kernel is not able
to change the control bit. Hence kernel is not able to control the
IRQ on the pin when required.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Ref: commit 38b8bf02d8
("intelblocks: Add function to program GPE_EN before GPIO locking")
This patch skips the locking for GPP_F14 to allow kernel to
configure it later during reboot or shutdown as required.
BUG=b:254064671
BRANCH=None
TEST=Shutdown works on Skolas and Brya board with the patch.
Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is an existing issue for skolas boards where board wakes up
from shutdown immediately due to touchpad wake signal.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Ref: commit 38b8bf02d8 ("intelblocks: Add function to program GPE_EN before GPIO locking")
Later issue was found to be with GPP_F14 configuration for skolas
boards. While shutting down, kernel is not able to disable IRQ for
touchpad due to GPE_EN register getting locked and it is preventing
shutdown of the board.
This patch skips the locking for GPP_F14 to allow kernel to
configure it later.
BUG=b:254064671
BRANCH=None
TEST=Shutdown works on Skolas board with the patch.
Nissa Bug: 234097956
Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: I09cf1af1f5ab11b06073755374ee8a306984d557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72426
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Otherwise configurations in src/mainboard/ocp/tiogapass/Kconfig
cannot be selected by
make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass
Change-Id: I88d5619269a6a9c09e84061642206a17c91db042
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Wellsburg is IFDv2 compatible in most fields, but not in all.
It only has 8 regions and the flash master bits match the defines for
IFDv1 and thus has an "IFDv1.5" descriptor.
Add a new enum for IFDv1.5 descriptor and use them to properly operate
on this IFD.
The 'SPI programming guide' is inconsistent and mentions 6 regions
in one place, but 7 regions in another chapter. Tests showed that it
actually supports 7 regions.
Add support using the -p argument to specify Wellsburg platform.
The previous patch made sure that only 8 regions are used and that no
corruption can happen when operating in IFDv2/IFDv1.5 mode.
Tested on Intel Grangeville.
Documents used:
Intel Document Id: 516552
Intel Document Id: 565117
Change-Id: I651730b05deb512478d059174cf8615547d2fde4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Co-developed-by: Julian Elischer <jrelis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
With New Crypto upgrade we need to have 1 block of 4Kb increase in
romstage, by which we can see an improvement of Boot performance
by 100 msec.
BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board
Boot performance improved by 100 msec observed.
Change-Id: I9f5c8a79993fc1c529fae5cea4c4182663643ddd
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72646
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
During boot, gpi_firmware_load gets called twice because there are
2 serial engines. Thus gsi_fw blob is also decompressed twice and is
written to base addresses of SEs. This is redundant.
Perform the decompression once on first call and save the header
in static variable which can be reused in next call.
BUG=b:262426214
TEST=Validated on qualcomm sc7280 development board
Saving of 80ms observed while testing with 130 boot cycles.
Change-Id: If98a3974f0791dffdf675c02cc28375d0485c485
Signed-off-by: Vijaya Nivarthi <vnivarth@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71927
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ic42c67163fe42392952499293e91e35537cb9147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I34d3c4a60653fe0c1766cd50c96b8d3fe63637d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The D-state list lists the devices with the corresponding
D-state that the devices should be in, in order to enter LPM.
DPTF is not mentioned in Intel's document 595644 as one of
the devices.
This CL removes it to avoid a potential error seen in ADL
devices as mentioned in commit 3fd5b0c4cdeb ("soc/intel/adl:
remove DPTF from D-states list used to enter LPM")
TEST=Built and tested on Rex, saw SSDT generated properly.
BUG=b:231582182
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I9192ed9a7fb59ebba14f6d5082b400534b16ca72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72603
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The 4.19 release notes included a list of outstanding issues formatted
as a markdown table, which is not supported by Recommonmark. Reformat
as an embedded reStructuredText table.
- The table of boards supported on the 4.18 branch did not include row
separators causing all rows to be rendered in a single row of cells.
- Technotes/console.md had a typo in the rST table formatting which
generated warnings in the Sphinx build, causing the table to not be
rendered in the resulting html.
Change-Id: I86e2c5d6d20e6002b87efc4688fc11b24b341227
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Currently there is a problem, where two Displayports are not working. To
be precise: TCP0 and TCP1 (Type-C Port 0/1) are not working.
Setting the lane count of the TCP0 and TCP1 to x1 works fine.
Setting the lane count of the TCP0 and TCP1 to x2 does not work.
Setting the lane count of the TCP0 and TCP1 to x4 does not work.
The reason for that is currently unknown.
This change sets the lane count of the TCP0 and TCP1 Port to x1 length
in the VBT binary.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I182b528275152bf5adcb01a56816afd65674aed3
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72610
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Markdown does not render newlines unless there is an empty line in
between the lines of text. Several command examples and a list were
missing these empty lines, causing their content to be rendered inline
with the preceding text.
Fix this by adding triple backticks around code blocks and bullet points
to rows of text in a list.
Change-Id: I9c1d2b81acdeb378346c68bced0cdbfeeb81bf26
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72625
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In CB:71614 Kyösti pointed out that ACPI_GPE0_BLK is the wrong address
to assign to proc_blk_addr; the correct one would be ACPI_CPU_CONTROL.
When looking a bit closer into this, it turned out that
acpigen_write_processor is generating deprecated AML opcodes, so replace
the acpigen_write_processor call with a call to the newly added
acpigen_write_processor_device function that also doesn't have the
proc_blk_addr and proc_blk_len parameters. The information about the IO
port for entering C-states is already written into an SSDT by
acpigen_write_CST_package which is likely also the reason why the wrong
proc_blk_addr value wasn't noticed for a very long time.
TEST=Mandolin still boots Ubuntu 22.04 LTS and Windows 10 and no
possibly related errors show up. Linux gets the expected C-state
information from the _CST package inside the processor device scope.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie67416e19e431029dd12da66ad44ddfa8586df03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The ACPI PROCESSOR_OP has been deprecated in ACPI 6.0 and dropped in
ACPI 6.4 and is now permanently reserved. As a replacement, DEVICE_OP
with the special HID ACPI0007 should be used instead. This special HID
was introduced in version 3 of the ACPI spec. To have a function to
generate this, acpigen_write_processor_device is introduced. The CPU
index is used as UID which can be assumed to be unique.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb0da903a972be134bb3b9071f81b441f60917d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72469
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This register isn't used in coreboot and isn't defined in the Picasso
PPR #55570 Rev 3.18.
To enter a lower C-state, a read request to a special IO port is done.
The base address of this group of IO ports is configured in
set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave
the CPU. IIRC trying to put the MMIO mapping for entering the lower
C-states into the _CST package didn't work as expected when it was tried
on I think Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I7dfd331e70f6d03c88248ca5147dbe6785a8e69d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
It turns out that the [0xfa000000-0xfaffffff] range conflicts with
some North TraceHub address space ranges ([0xfad00000-0xfadfffff] and
[0xfacfc000-0xfacfffff]).
Experiments have established that this conflicting range results in an
unpected PIPE A underrun issue reported by i915 and some visible
flickers on the display during boot.
The [0xf0000000-0xffffffff] range is a crowded memory space with
resources statically assigned to some devices but also some ranges
used at various point in the boot flow by the FSP.
To not run into any other potential conflicts, we want to pick a
unused memory space. But at this early stage of the boot, we do not
have full knowledge of what memory space is going to be used by the
FSP. As a result, we decided to pick the [0xaf000000-0xafffffff] range
as:
1. It does not conflicting with any coreboot memory space usage
2. It is the address the FSP uses by default for GFX MMIO BAR0 and as
such should not conflict with any FSP memory space usage.
BUG=b:264648959
BRANCH=firmware-brya-14505.B
TEST=No flickers observed on boot
Change-Id: I6a00350ff4007bb7692d2ff6598b946cc6123302
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72605
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
