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42858 Commits

Author SHA1 Message Date
Fred Reitberger
267edecccb soc/amd/morgana/Kconfig: Remove TODO after review 
Remove more TODO comments after reviwing against morgana ppr #57396, rev
1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7fd9666a69d9a2b0902fa28ab0af0187198297ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70466
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 19:39:10 +00:00
Felix Held
c4f5241e66 soc/amd/common/block/espi_util: drop unneeded check in espi_get_config 
Since soc_get_common_config will either return a valid pointer or cause
a linking error, this function will also return a valid pointer or cause
a linking error, so no need for additional runtime checks.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2022-12-14 17:58:08 +00:00
Felix Held
993092039b soc/amd/*/config: drop invalid comment 
Since commit 28e61f1634 ("device: Use __pci_0_00_0_config in
config_of_soc()") config_of_soc() was changed form being an actual
function to a macro for the __pci_0_00_0_config struct pointer generated
by util/sconfig. This change didn't only improve linker optimizations,
but also turned runtime errors into link-time errors, so it's guaranteed
that __pci_0_00_0_config won't be NULL and config_of_soc() won't
"return" NULL.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id99ceaa9f7a70788da3f3068fb3da92d34fb6361
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70732
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2022-12-14 17:57:45 +00:00
Felix Held
687ec6bd72 soc/amd/common/block/espi_util: make espi_set_initial_config non-fatal 
Improve the espi_set_initial_config implementation so that a failure in
there due to an invalid configuration won't call die() and stop booting
at this point, but return an error to the caller so that the rest of the
eSPI configuration will be skipped.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2022-12-14 17:07:19 +00:00
Felix Held
84429e092f soc/amd/common/block/lpc/espi_util: make eSPI pin setup failure nonfatal 
Improve the eSPI pin configuration setup so that a failure in there
won't call die() and stop booting at this point, but return an error to
the caller so that the rest of the eSPI configuration will be skipped.
This will prevent an early boot failure if the EC is missing or the eSPI
interface is in a non-functional state. Also slightly shorten the
function names so that the code still fits into 96 chars.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
 2022-12-14 16:05:50 +00:00
Arthur Heymans
4f2b5a5dbd device/cpu_device.c: Zero initialize struct 
Don't rely on this being 0.

Change-Id: I7c0d16b6a265bf9c7abcfdf2f18a43706ee03ea1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69752
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-14 13:52:00 +00:00
Arthur Heymans
db65dd60fb cpu/x86/mp_init.c: Improve AP entry point 
Make sure that a pointer exists before dereferencing it.

Change-Id: I1a9833bb9686451224249efe599346f64dc37874
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-14 13:51:40 +00:00
Sridhar Siricilla
f9ee35ea34 soc/intel/common: Add helper function to get DP mode 
The patch adds helper function to get the DP mode.

TEST=Build the code for Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-12-14 13:35:36 +00:00
Arthur Heymans
e64b8ac1e7 cpu/intel/206ax: Fix generating C state entries 
The struct device passed to this function is the cpu cluster and not
individual lapic. This fixes a regression introduced by
cdb26fd (cpu/intel/model_206ax: Remove fake lapic device)

Change-Id: I586e13a723303b8d639d526a175bd6828465a607
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2022-12-14 13:31:09 +00:00
Subrata Banik
d34364bdea soc/intel/alderlake: Utilize CPU_BCLK_MHZ over dedicated macro 
This patch drops the redundant macro to define CPU BCLK and instead
uses `CPU_BCLK_MHZ` config to calculate the
`smbios_cpu_get_max_speed_mhz`.

TEST=Able to see max cpu speed is correct in smbios table while trying
on Google/Kano.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 07:03:16 +00:00
Subrata Banik
ba6e66328b soc/intel/meteorlake: Drop NEM support 
This patch drops NEM support from MTL and enables eNEM support.

BUG=b:217130861
TEST=Able to build and boot Google/Rex in eNEM mode.

Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-14 07:02:31 +00:00
Subrata Banik
43004211e2 soc/intel/meteorlake: Add required configs to enable eNEM 
This patch combines all required configs under one umbrella config
named `METEORLAKE_CAR_ENHANCED_NEM`.

MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not
selected.

BUG=b:217130861
TEST=Able to build and boot Google/Rex.

Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-14 07:01:59 +00:00
Subrata Banik
8e158597f9 soc/intel/meteorlake: Reorg TCSS related configs 
This patch moves all required TCSS related configs under one umbrella
config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will
help in future to deselect the TCSS support for MTL SoC SKUs.

TEST=Able to build and boot Google/Rex.

Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 07:01:48 +00:00
Subrata Banik
b5fc0c4088 drivers/wwan/fm: Fix typo 
This patch fixes a typo by adding `Arg0 = 0` to define warm reset.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I92b81697a254c9dab127b200174d32554db1b5cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70721
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2022-12-14 06:51:15 +00:00
Subrata Banik
6ed431589b vc/intel/fsp/mtl: Update header files from 2404_00 to 2431_80 
Update header files for FSP for Meteor Lake platform to
version 2431_80, previous version being 2404_00.

FSPM:
1. Address offset changes

FSPS:
1. Address offset changes

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 06:47:47 +00:00
Subrata Banik
10929ef008 soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable 
This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.

This patch is backported from
commit fad1cb062e (soc/intel/alderlake:
Fill ucode loading UPD if USE_FSP_MP_INIT enable).

Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 06:35:11 +00:00
Subrata Banik
b25aeb5937 soc/intel/meteorlake: Remove FIXME as SkipMpInit UPD has deprecated 
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP
doesn't like to allow an option for boot firmware to perform CPU feature
programming being independent of FSP.

Change-Id: I6447937838ab91551d172936cbb4201ea86a614b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 06:34:16 +00:00
Subrata Banik
95fc5d776a soc/intel/meteorlake: Drop enable_bios_reset_cpl() function 
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset
CPL before performing Graphics PM init (as part of FSP-S), hence,
enable_bios_reset_cpl() function getting called inside systemagent.c
is meaningless.

Also, drop 1ms delay after setting the BIOS reset CPL.

This patch is backported from
commit 3f980ca7be (soc/intel/alderlake:
Drop enable_bios_reset_cpl() function).

Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
 2022-12-14 06:33:23 +00:00
Subrata Banik
decb9717ce soc/intel/meteorlake: Enable VMX and VTD 
Drops the `FIXME` comment and relevant code as this patch enables
VMX and VTD.

This patch also fixes the problem of additional reboot on every warm
boot due to overriding the CPU soft-strap.

TEST=No extra reboot seen while issuing warm reset from kernel
console.

without this patch:
950:calling FspMemoryInit		1,225,259 (20,537)
951:returning from FspMemoryInit	10,334,707 (9, 109,447)

with this patch:
950:calling FspMemoryInit		1,225,259 (20,537)
951:returning from FspMemoryInit	1,334,707 (109,447)

Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 06:33:09 +00:00
Eran Mitrani
988d3eefa6 mb/google/hatch/dratini: increase power enable to reset deassert delay 
With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.

TEST=tested on dratini device and observed the issue is resolved.
BUG=b:260253945

Change-Id: I5c3edbc6ac90d5042c2d3c5b01573d4bb1ea676d
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70666
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 03:46:09 +00:00
Tarun Tuli
0f0a43c9b1 mb/google/poppy: Add support for a variant finalize function 
Add a hook to allow a variant finalize to be called at the end of
ramstage.

BUG=b:245954151
TEST=Builds successfully

Change-Id: I00c091051e3499ca94b286d7fbe0a7a8bd38e635
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70319
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-14 03:31:47 +00:00
Felix Singer
fa0709663b sio/winbond/w83627hf/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I6858ddaa8b70194ffdd3b4edcb0ee57aec262b48
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:53:57 +00:00
Felix Singer
84e6123d7e soc/intel/braswell/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I2dd154c3d4e152a14783ea82e08a7d1257abebc3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:53:09 +00:00
Felix Singer
3dc4d84586 soc/intel/cannonlake/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I9ddb71d93781c813a69dc72ce0589ffaea7b64c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:52:52 +00:00
Felix Singer
8cc2962b12 soc/intel/icelake/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I12560d151d26186e1f4eb0165aa8cef33b7a16aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:52:23 +00:00
Felix Singer
476fe6ae7e soc/intel/baytrail/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: Ic171f3343bb35e43be5fdb50c5c926eede6a1d93
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-14 00:52:05 +00:00
Felix Singer
3e90ce547c mb/google/cyan/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I349d1e7d3027097c5db4da96e2376831fff61b04
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:51:30 +00:00
Felix Singer
1151088c02 mb/google/skyrim/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: Ib75ccc10c8086086f5db4ced1163b74c9835364b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:51:18 +00:00
Felix Singer
a006259e6f mb/google/slippy/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I950d776a712a104f2caed614886ce2527028ead7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:51:01 +00:00
Felix Singer
1bb621c002 sio/winbond/w83667hg-a/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I3809880312af4736407e361da53f0424280e43d4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:50:42 +00:00
Felix Singer
a61e6546f6 mb/google/kahlee/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: Ib2ba6b5c14f6699dc6c0734724a6784e3400a467
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:50:02 +00:00
Felix Singer
69b48d8231 mb/google/jecht/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: If6c37cc2ce51780e0bae007d884d8f77b20847fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:49:50 +00:00
Felix Singer
c64c9cd5fa mb/aopen/dxplplusu/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I04f61df6b651058060b88e5f5679a0dd5270e66d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:49:20 +00:00
Felix Singer
4da79a7f25 ec/smsc/mec1308/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I0a419c861e84cd96e8337957dc62a7ca5b981e14
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:49:01 +00:00
Felix Singer
612801d0f8 ec/quanta/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I00a6ece73048209861221cba5f2c7381adfa54b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:48:46 +00:00
Felix Singer
ff6b3af113 ec/google/chromeec/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I2cdb1c9ae3a33bfc72767ff60d8948054d4e151a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:48:30 +00:00
Felix Singer
f45a6c2a50 ec/lenovo/h8/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I1c68816f47aa3ed0ab3bf55d4cfde71d5838d051
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:48:07 +00:00
Felix Singer
2f308d4957 sb/intel/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I94b2e6ecb90a2616e184ae9331c397c75089e373
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:47:52 +00:00
Felix Singer
b26e255877 mb/51nb/x210/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: Ic0ae4903546446322c2c47cab00de4c3af6c9d98
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:46:56 +00:00
Felix Singer
facf7d077c superio/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: Ibbecba97dd1628889539c2962dd31964c252c8bb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:46:41 +00:00
Felix Singer
18af706d50 vc/google/chromeos/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: I8b2d97063ba199274c1072ba3a12613162a17ef1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-14 00:46:20 +00:00
Felix Singer
52f46525b4 drivers/intel/gma/acpi: Replace Store(a,b) with ASL 2.0 syntax 
Replace `Store (a, b)` with `b = a`.

Change-Id: Ifd3a814228df6a399fe1110abf5b5bc18e6fd6d2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-12-14 00:46:03 +00:00
Fred Reitberger
a6514e2b1f soc/amd/morgana: Enable GPP clk req disabling 
Enable GPP clk req disabling on morgana after reviewing against morgana
ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-13 17:43:11 +00:00
Jeff Li
3de39fa36f soc/intel/common/block: add definition of GPIO configuration 
Add two macros:
 - PAD_CFG_NF_OWNERSHIP()
 - PAD_CFG_GPIO_OWNERSHIP()

to support setting the Host Software Ownership (own) fields.

Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com>
Change-Id: Ia3f2ad8658b751156456b69366fa4b1badb8b595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70421
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
 2022-12-13 17:42:03 +00:00
Felix Held
2557d02eee mb/google/guybrush,skyrim: use gpio.h include everywhere 
Now that gpio.h will only include the defines in the IASL case, gpio.h
can be included instead of soc/gpio.h in the files that will be directly
or indirectly included in the DSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-13 15:23:52 +00:00
Felix Held
acf96dfcdc include/gpio: skip everything but soc/gpio.h include in ASM & ACPI cases 
When gpio.h gets directly or indirectly included in the DSDT ar an
assembly file, everything but the preprocessor defines for the GPIOs
shouldn't be included to keep IASL or the assembler happy.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I046ed87d3947ba5b1fcd0bdd4cffcda57bc13404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70509
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-13 15:23:37 +00:00
Elyes Haouas
3cd89a003b vc/eltan/security/mboot/Makefile.inc: Remove path to non-existent folder 
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ie2c4a6c2bb55af56cb6e0b013b1a2ed9baa787ef
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70460
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-12-13 15:19:58 +00:00
Reka Norman
4ae5873e7f mb/google/nissa/var/nivviks,yaviks: Add DmaProperty for ISH 
On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on nivviks and yaviks.

BUG=b:259716145
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.

Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA-FQ

After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA

Change-Id: Iaddb24580bda77df0c70ff58eb098213f8b509ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:52:57 +00:00
Reka Norman
6419fbf193 drivers/intel/ish: Allow adding DmaProperty to _DSD 
On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Allow adding
DmaProperty to the _DSD of the ISH device. This will result in the
kernel marking the device as untrusted.

BUG=b:249846505
TEST=Check SSDT is correct, and kernel detects the DmaProperty and
firmware-name properties.

SSDT entry on yaviks with both add_acpi_dma_property and firmware_name
set in devictree:
    Scope (\_SB.PCI0.ISHB)
    {
        Name (_DSD, Package (0x04)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
            Package (0x01)
            {
                Package (0x02)
                {
                    "firmware-name",
                    "adl_ish_lite.bin"
                }
            },

            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    }

Change-Id: Ie1539fc757e72e995e98c3ecf83e705e3bede8c0
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-12-13 14:52:37 +00:00
Fred Reitberger
0423bce8e8 soc/amd/morgana: Update pci int defs 
Update pci int defs per preview of next ppr after rev 1.52, #57396
Update birman and mayan mainboards to remove deleted PIRQs.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-12-13 14:38:06 +00:00