Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: I1a55df754c711b2afb8939b442019831c25cce29
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: Ie86822f22aa5899a7e446398370424ca5a4ca43d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Fix the two issues below.
SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:49:18
ubsan: unrecoverable error.
SB800: sb_Before_Pci_Init
shift out of bounds src/vendorcode/amd/cimx/sb800/PCILIB.c:66:18
ubsan: unrecoverable error.
Found by: UBSAN
Change-Id: Id42e62d35f59793bad10998f14422ab7fb4fc029
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Currently, running abuild in a fresh checkout without having built the
toolchain results in the following confusing behaviour:
1. Run abuild. It fails due to the missing coreboot toolchain, and the
error message suggests running `make crossgcc`.
2. Run `make crossgcc`. It succeeds.
3. Re-run abuild. It still fails due to a missing coreboot toolchain.
This happens because the first abuild run generates an xcompile file
which uses the system toolchain. The second abuild run doesn't
regenerate the xcompile, so it still fails due to the non-coreboot
toolchain.
To avoid this confusing behaviour, regenerate the xcompile file every
time abuild is run.
BUG=None
TEST=Perform the steps above in a clean checkout. The second abuild run
now succeeds.
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I78a7702c45cecbfe8460ec55df03741e5ced94b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change provides helper macros for generating pointer name and
weak pointer definition for devices using alias names. This will be
helpful for developers to reference the device pointer with alias
names used in the device tree.
Change-Id: I3a5a3c7fdc2c521bac9ab3336f5a6ebecd621e04
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change uses _dev_${ALIAS_NAME} as the name for `struct device` if
the device has an alias. In addition to that, it emits
_dev_${ALIAS_NAME}_ptr which points to the device structure. This
allows developers to directly reference a particular device in the tree
using alias name without having to walk the entire path. In later CLs,
mainboards are transitioned to use this newly emitted device structure
pointers.
Change-Id: I8306d9efba8e5ca5c0bda41baac9c90ad8b73ece
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The input buffer to the buffer_to_fifo family of functions is only read,
so it can be a const pointer. (Also, remove the MIPS check in libpayload
for these functions... the MIPS architecture has been removed a while
ago.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
SBI comes with its own memset implementation (under a slightly
different name) that gcc11 "helpfully" tries to replace with a call
to memset(). Since we don't provide a memset, the linker isn't happy,
so prevent gcc from doing that.
Change-Id: I3459a519d46a123f873306000b8b2261bd64e0c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We never call console_init from asm, so we don't need the asmlinkage.
This allows us to remove the arch/cpu.h include since we only needed it
for the asmlinkage #define.
BUG=b:179699789
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9a7895d4f5cba59f6b05915fa4d6c6fd6ab85773
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57568
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that primus can successfully
boot into OS with non-serial coreboot.
BUG=b:199967106
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I9c66efe96515347502d059556052c764c1be5d09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When the century byte was reserved, the debug_level was accidentally
converted from an enum to a hidden value. Change it back to an enum.
Fixes: f05bd8830d ("mb/system76/*: cmos.layout: Reserve century byte")
Change-Id: Id88a7aed7b2fc793fd003db5b45f3f201b1a7630
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
When using a debug build of the FSP, the FSP-M binary is larger than the
memory region we have allocated for it, so increase the size to make the
binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so
that it starts right after the the FSP-M memory region.
TEST=coreboot builds now successfully when using a debug version of the
FSP
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently there are two versions of spd_tools: one for LP4x and one for
DDR4. This change is the first step in unifying these into a single
tool.
This change implements a unified version of the spd_gen tool, by
combining the functionality currently in lp4x/gen_spd.go and
ddr4/gen_spd.go. The unified version takes the memory technology as an
argument, and generates SPD files for all platforms supporting that
technology.
BUG=b:191776301
TEST=Compare the SPDs generated by the old and new versions of the tool
for all supported platforms. For reference, the test script used is
here: https://review.coreboot.org/c/coreboot/+/57511
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I7fc036996dbafbb54e075da0c3ac2ea0886a6db2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
To save the space for FW, some of the FWs are going to be defined as
LVL2 entries. To be compatible to "flattened" layout, we still drop
the LVL2 entry to level1 if there is only one level.
Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators
are connected to the DRAM. With the exception of an early Skylake RVP
board (which doesn't have coreboot support), mainboards using DDR3 or
LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with
DDR4 should set `CaVrefConfig` to 2. MRC uses this information during
memory training, so it is important to use the correct value to avoid
any issues, such as increased power usage, system instability or even
boot failures.
However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2.
Although they can boot successfully, it's not optimal. For boards that
set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2.
Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
vboot_reference is introducing a new field (ctx) to store the current
boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged
in both vboot flow and elog_add_boot_reason in coreboot.
In current steps of deciding bootmode, a function vb2ex_ec_trusted
is required. This function checks gpio EC_IN_RW pin and will return
'trusted' only if EC is not in RW. Therefore, we need to implement
similar utilities in coreboot.
We will deprecate vb2ex_ec_trusted and use the flag,
VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag
in coreboot, verstage_main.
Also add a help function get_ec_is_trusted which needed to be
implemented per mainboard.
BUG=b:177196147, b:181931817
BRANCH=none
TEST=Test on trogdor if manual recovery works
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make neovim the default editor and create an alias for vim.
The NixOS module for neovim is currently broken. Thus, add a note to
`description.md` to switch to that later.
Change-Id: I9345a6e32f3035565e55e50579c97121b4987d83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57393
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
