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34174 Commits

Author SHA1 Message Date
Felix Held
4ef37ae68d soc/amd/cezanne/data_fabric: add ACPI names and SSDT entries 
Additionally to the PCI IDs of Cezanne it also handles the Renoir ones.
The main difference between those two is that Renoir has two core
complexes while Cezanne only has one core complex. I haven't seen
incompatible changes between those two though, so for example the fabric
IDs are the same and the one that's only present in Renoir is just not
used in Cezanne. Also adding the ACPI parts for those don't have
anything to do with those differences.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b2517bc15d872f41183a33857333f1972ff2cb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-16 00:08:06 +00:00
Paul Menzel
c4062c78a9 device: Add unit to Kconfig option name: PRE_GRAPHICS_DELAY_MS 
It’s good practice to put the unit into the name.

Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-15 17:05:18 +00:00
Patrick Georgi
6b688f5329 src: use ARRAY_SIZE where possible 
Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 11:30:40 +00:00
Elyes HAOUAS
036d66be05 soc/qualcomm/sc7180: Remove unused <console/console.h> 
Change-Id: Ie71cc6f79db9f2d722f9931e887f309e0bc9ce0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50533
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:51:59 +00:00
Elyes HAOUAS
b1db6744b6 commonlib/cbfs.c: Remove unuse <console/console.h> 
Change-Id: I263db3c3d26a8690b3fa493cb2e317000c4dc89d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50532
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:51:24 +00:00
Elyes HAOUAS
2ed14dbc80 sb/amd: Remove unused <console/console.h> 
Change-Id: I8c0a40a14d0a9050b83fe5e9988db70b7f94b81c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50531
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:51:10 +00:00
Elyes HAOUAS
e9514a43ee soc/qualcomm: Remove unused <console/console.h> 
Change-Id: Idd93ed91e854c8775cbcf721e4e332aef7b36e42
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50530
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:50:47 +00:00
Elyes HAOUAS
804bb522a3 soc/mediatek: Remove unused <console/console.h> 
Change-Id: If025d4c0b2ba9868d8df699fcddfcec349cdc0ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50529
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:50:23 +00:00
Elyes HAOUAS
7cb4cb64ba soc/intel: Remove unused <console/console.h> 
Change-Id: I630b7b0b1d564bcd99358caaaef4afd78c22866c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50528
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:50:09 +00:00
Elyes HAOUAS
f81d09d653 src/security: Remove unused <console/console.h> 
Change-Id: I2b81a57ded80ef9c5cbdff06d8ca9d6b4f599777
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50526
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:49:53 +00:00
Elyes HAOUAS
6f35c53bbb src/nb: Remove unused <console/console.h> 
Change-Id: I55aa05f72e06b509c85f0754320c389de7e75f8d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50525
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:49:08 +00:00
Elyes HAOUAS
39239e6fff src/mb: Remove unused <console/console.h> 
Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:48:53 +00:00
Elyes HAOUAS
ca77b35e4e src/drivers: Remove unused <console/console.h> 
Change-Id: I38d565f82d078cb75f74f8502fcafdedd907b97d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50523
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:48:39 +00:00
Elyes HAOUAS
da00a298f4 src/device: Remove unused <console/console.h> 
Change-Id: I30ed9661d8e84be49d362baafbb2bc624952c287
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50522
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:48:28 +00:00
Elyes HAOUAS
f6c4eeab1a src/arch: Remove unused <console/console.h> 
Change-Id: Idb80b21bb5dc4b461f89a3414d51b7d98a8328d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50521
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 10:48:12 +00:00
Kyösti Mälkki
e050a01a90 mb/lippert/frontrunner-af: Drop OSFL method in ASL 
Method only set variable OSRV, which nobody evaluates.

Change-Id: I76d86af8ef6b75531f11612935dd097ee1e1a388
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2021-02-15 10:01:49 +00:00
Angel Pons
59626b8670 drivers/spi: Stop using a variable-length array 
Only the call in `spi_flash_cmd_write_page_program` uses non-constant
values for the array length. However, the value for `data_len` has an
upper bound: `flash->page_size` is set to `1U << vi->page_size_shift`
which depends on the flash chip vendor info, and the largest value it
can currently have is 8. Thus, the maximum page size is currently 256.

Define the `MAX_FLASH_CMD_DATA_SIZE` macro to place an upper bound on
the amount of data that can be written in one command. Then, use this
value to allocate a fixed-size buffer in `spi_flash_cmd_write`. Also,
add a check to prevent buffer overflow problems. Finally, ensure that
the `spi_flash_cmd_write_page_program` function always writes no more
than 256 bytes of data when using the `spi_flash_cmd_write` function.

Tested on Asrock B85M Pro4 (Winbond W25Q64FV), MRC cache still works.

Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2021-02-15 09:58:05 +00:00
Angel Pons
9cf9b85476 soc/intel/broadwell/pch: Use Lynxpoint GPIO code 
This allows dropping `gpio.c` from Broadwell.

Change-Id: I6b34e11f849cdf01e402fe79d078711af94e1ec0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50081
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:54:28 +00:00
Angel Pons
52e48b56e2 broadwell boards: Switch to Lynxpoint GPIO headers 
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because
Lynxpoint uses a different value. Also drop unnecessary includes.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:53:49 +00:00
Angel Pons
733f03d6f4 soc/intel/broadwell/pch: Prepare to drop gpio.h 
Use `lp_gpio.h` from Lynxpoint instead. Subsequent commits will update
the mainboards and then drop all GPIO code from Broadwell.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: Idef89037c2ca781ac3e921abb4b3dc3f7c4b3b5f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50079
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:53:28 +00:00
Angel Pons
9602a4ac77 mb/google/auron/var/samus: Replace define with literal 
The `GPIO_OUT_HIGH` macro is not present on Lynxpoint headers.

Change-Id: I12dd065bee49097c602febf18c6c9940ecec5106
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50078
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:52:47 +00:00
Angel Pons
e80fb4bd30 mb/google/jecht/var/tidus: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: I1521a51455e2aa148298853bb1878e82b9f0c368
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50077
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:52:03 +00:00
Angel Pons
c1dacb9a41 mb/google/jecht/var/rikku: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Rikku remains identical.

Change-Id: I4d5bec4ec18b645a14d21fbee7334761901a30df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50076
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:51:48 +00:00
Angel Pons
19a3c49539 mb/google/jecht/var/jecht: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Jecht remains identical.

Change-Id: I193fe1471b8ade5d03e874f92425962c1ed960c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50075
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:51:37 +00:00
Angel Pons
79520c6e94 mb/google/jecht/var/guado: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Guado remains identical.

Change-Id: I3a806d07b0ca147492b90feaf90235ed919b1bb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50074
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:51:23 +00:00
Angel Pons
c26b567478 mb/google/auron/var/samus: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Samus remains identical.

Change-Id: I465457ea8e9a9716121eacc0f6d64de463f41d89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50073
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:51:10 +00:00
Angel Pons
4dadeb3f22 mb/google/auron/var/lulu: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Lulu remains identical.

Change-Id: I0f0a584b3354971ee8d478fd17825e498ff3e423
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50072
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:50:56 +00:00
Angel Pons
7ad729c136 mb/google/auron/var/gandof: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Gandof remains identical.

Change-Id: I168fcad7088706ca5b21f5fbf6790b13054499e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50071
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:50:36 +00:00
Angel Pons
d1ff7e43b5 mb/google/auron/var/buddy: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Buddy remains identical.

Change-Id: I6e6256a9cc88c9d0743150bfdf12b1b482fe157d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50070
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:50:21 +00:00
Angel Pons
6259aeb86e mb/google/auron/var/auron_yuna: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Auron Yuna remains identical.

Change-Id: I17e6bf20114f43da2897ec320ca26d8c6f6a4b09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50069
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:49:42 +00:00
Angel Pons
bb95f24115 mb/google/auron/var/auron_paine: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Google Auron Paine remains identical.

Change-Id: I00b9184fe6f002c3e089c9fbc815862d60e7694f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50068
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:49:17 +00:00
Angel Pons
2d11f71220 mb/intel/wtm2: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Intel WTM2 remains identical.

Change-Id: I422421cc3c336a7a1aceaff7b37ab7c82f64a03f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50067
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:48:46 +00:00
Angel Pons
2126aecb32 mb/purism/librem_bdw: Switch to Lynxpoint GPIO macros 
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I573cd439e8284d84036e71615944f7a195155593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50066
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:48:32 +00:00
Tim Wawrzynczak
d4749184c2 mb/google/brya: Add EC I/O decode windows 
BUG=b:180013349
TEST=console shows successful EC <-> SoC communications

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie09dcfa8b0de2706ffc236a978dc159594e327c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-02-15 08:25:47 +00:00
Tim Wawrzynczak
ad21d6bfca mb/google/brya: Enable cr50 support 
Add Kconfig options and devicetree entries for cr50 TPM.

BUG=b:180017621
TEST=verify (via console) successful cr50 communications in
verstage and payload (depthcharge).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I80e27d0377960fb81f9149efb6f062d06432d40d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-02-15 08:25:36 +00:00
Mathew King
91a2cd4770 mb/google/guybrush: Configure non-native function GPIOs 
Second pass GPIO configuration to enable the non-native function
GPIOs based on the guybrush Proto 0 reference schematic 0210.

BUG=b:177909472
TEST=builds

Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-02-15 08:22:53 +00:00
Raul E Rangel
f41ca1ed76 soc/amd/cezanne: Add uart.c to smm so we can support DEBUG_SMI 
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife43352db564654ed538383a157431ee10856518
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-15 08:22:27 +00:00
Angel Pons
ec38570ead nb/intel/sandybridge: Correct description of QCLK 
QCLK means "quadrature clock", and is equivalent to one half of a full
clock cycle (tCK). Fix the comment. The `QCLK_PI` value is still valid.

Change-Id: I7089fc32381addc280a71761a377075f107b5c62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49363
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:21:33 +00:00
Patrick Rudolph
fc36e9fb0e soc/intel/*: Move prmrr_core_configure 
Move prmrr_core_configure before clearing MCEs.

This is required for the following patch in order to update microcode
after PRMRR has been configured, but before MCEs have been cleared.

According to Document 565432 this should be no issue in regards to
SGX activation.

Change-Id: Id2808a3989adff493aaf4175cbeccd080efaaedf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-15 08:20:19 +00:00
Angel Pons
aacbd66a85 sb/intel/lynxpoint: Clean up lp_gpio.h 
Move `mainboard_gpio_map` declaration inside header and reorder some
function declarations. This is to align the header with Broadwell.

Change-Id: I436d7fdabf8d574e5dd2787fb6097f384cc8e453
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50065
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:19:14 +00:00
Angel Pons
f76822a75c soc/intel/broadwell/pch: Rename GPIO identifiers 
Rename structs, types and functions to match Lynx Point's names.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-15 08:19:03 +00:00
Maxim Polyakov
19d4364ed6 intel/xeon_sp/util: Use get_stack_busno instead of get_cpubusnos 
This function is more convenient to get the value of a single bus number
than get_cpubusnos(). Now get_cpubusnos is not used anywhere, so remove
it.

Change-Id: I71c06c2d69344d97e48609e67a3966ed8c671152
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-15 08:18:07 +00:00
Felix Held
b03dc9c12b soc/amd/picasso: always include PSP secure OS in amdfw 
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-02-14 21:58:10 +00:00
Angel Pons
6ab87664b7 arch/x86: Drop cstates pointer from CPU drivers 
Nothing uses this pointer anymore.

Change-Id: Id2dee8f4cb243114d6f7f7485402acb9b73b7900
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49808
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:57:13 +00:00
Angel Pons
e49dec45c8 cpu/intel/haswell: Constify ACPI c-state arrays 
Change-Id: I5538d8279392238e59aba99ade4b5fe13f250ca8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49805
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:57:00 +00:00
Angel Pons
618b9ade15 cpu/intel/haswell: Drop c-state table indirection 
Accessing it directly allows proper bounds-checking.

Change-Id: Ifb539051e4a91ddcdb5ffec4850dc2fb30482aea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49804
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:54:55 +00:00
Angel Pons
85790d028f cpu/intel/model_206ax: Drop c-state table indirection 
Accessing it directly allows proper bounds-checking.

Change-Id: I2582a7edf5fba28febe570bddccacb85a3269684
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:54:48 +00:00
Angel Pons
d8b9e562d0 cpu/intel/model_206ax: Replace generate_cstate_entries 
Leverage the existing `acpigen_write_CST_package` function.

Yes, bad devicetree values can trigger undefined behavior. The old code
already had this issue, and will be addressed in subsequent commits.

Change-Id: Icec5431987d91242930efcea0c8ea4e3df3182fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49093
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:54:39 +00:00
Felix Held
ea32c52a0e soc/amd/cezanne: add partial data fabric setup 
I'm not 100% sure yet if this code will be common for all AMD SoCs, so
I'll add a copy for Cezanne for now. This part of the code should
probably be reworked after the initial bringup of Cezanne anyway.

DF MMIO register configuration at the beginning of
data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       a3     fc00     febf
  1       a3  1000000 fffcffff
  2       a3     d000     f7ff
  3       a0        0        0
  4       a3     fed0     fed0
  5       a0        0        0
  6       a0        0        0
  7       a0        0        0

DF MMIO register configuration at the end of data_fabric_set_mmio_np:

=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx  control     base    limit
  0       a3     fc00     febf
  1       a3  1000000 fffcffff
  2       a3     d000     f7ff
  3     10a3     fed0     fedf
  4       a0        0        0
  5       a0        0        0
  6       a0        0        0
  7       a0        0        0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:48:23 +00:00
Felix Held
eb89ca67ef soc/amd/cezanne/include/iomap: add HPET base address 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72559147a3f86f0cb843b74af9b148d23229ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50623
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-14 21:48:03 +00:00