Kangheui Won
ac7ec27e5c
soc/amd/picasso: fix CBFS MCACHE on Zork
...
Zork platform was not booting with MCACHE enabled since psp_verstage
had following issues with MCACHE.
Fix all the issues and re-enable MCACHE for Zork.
* psp_verstage should call vboot_run_logic, not verstage_main.
vboot_run_logic calls after_verstage which handles RW MCACHE build.
* It should avoid low-level apis for cbfs access.
cbfs_map will build RO MCACHE if it's the first stage, while other
low-level apis won't.
* It should call update_boot_region before save_buffers
MCACHE should be transferred to x86 so we should build it before
calling save_buffers
BUG=b:177323348
BRANCH=none
TEST=boot Ezkinil
Signed-off-by: Kangheui Won <khwon@chromium.org >
Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-28 00:26:47 +00:00
Raul E Rangel
892a423de8
soc/amd/picasso/acpi: Remove DMA addresses for UARTs
...
This is not the correct way to specify the FixedDMA devices. I'm
removing for now since it adds confusion.
BUG=none
BRANCH=zork
TEST=Boot zork to linux and make sure UART still works
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I17b9c8dbe4f9c4b64ee1bd69cb9b30998e727632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-28 00:24:33 +00:00
Felix Held
613f9fc91f
soc/amd/cezanne/chip: add empty SoC device operations
...
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ic6321223b3b4b8d27ac696fdeeec75fd4bd1e6bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49952
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-28 00:16:55 +00:00
Felix Held
c963499791
soc/amd/cezanne: compress FSP binaries in CBFS
...
Compressing the FSP binaries in CBFS reduces the load time.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I0faf9a3937e4a5027eba6327a51060025971450f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49951
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-28 00:16:05 +00:00
Felix Held
58dfc6c479
Revert "mb/amd/mandolin: Clean up IRQ numbers"
...
This reverts commit 2a1638a9cefelix-coreboot@felixheld.de >
Change-Id: I7024b6ff1e772bbc89f810c766655a5887ed8b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49950
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-28 00:15:55 +00:00
Angel Pons
e2ec60f28b
nb/intel/haswell/haswell.h: Do not include pch.h
...
Avoid indirect header inclusion, include `pch.h` where necessary.
Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2021-01-27 21:28:18 +00:00
Felix Held
cbd5bb9cc7
soc/amd/picasso/chip: use switch/case statement in enable_dev()
...
The default case is only needed to make the compiler happy.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Idf54e7128f9e9d96f15ac7ab121f22621e033fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49941
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-27 19:25:36 +00:00
Kyösti Mälkki
78f52fb7d6
soc/amd/stoneyridge: Change set_sb_nvs_final()
...
Change-Id: I0de8033bae8c1dcfbc6fd7655ba748a3514e74e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-27 15:44:58 +00:00
Zheng Bao
b04405ff76
soc/amd/cezanne: Add UCODE firmware to CBFS
...
Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-27 15:43:55 +00:00
Zheng Bao
20f5687def
soc/amd/picasso: Remove the useless definition of UCODE_FILEs
...
UCODE files are integrated in CBFS now, instead of AMD firmware group.
Change-Id: I88fdd08ab400fad8e323251bb7dab4e4e01b0b88
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-01-27 15:41:18 +00:00
Zheng Bao
8516c219ce
soc/amd: Throw an error if FWM_POSITION_INDEX is empty
...
The empty string causes an undetectable build error.
Filter out the board which doesn't define this variable.
A great odds that the reason is the board doesn't set a
valid ROM size.
Change-Id: Iade1961460285acdec245c553c7b84014c30c267
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-01-27 15:40:50 +00:00
Amanda Huang
3765b50374
mb/google/brya/var/brya0: Use auto-generated Makefile.inc
...
This change adds mem_list_variant.txt that contains the only
memory parts used by brya0 for Proto-0 build and Makefile.inc
generated by gen_part_id.go using mem_list_variant.txt.
BUG=b:176491791
Change-Id: I3fe755564e7541a7abdfca0e5aa7fd786f5ca880
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-01-27 15:40:02 +00:00
Amanda Huang
4891e0b4d1
soc/intel/alderlake: Generate LP4x SPD files using gen_spd.go
...
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that can be
used with ADL-based mainboards.
BUG=b:176491791
Change-Id: Ie75e43833bf9ba6557fc59cf8b4a0358d495e56a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49919
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-27 15:39:55 +00:00
Kyösti Mälkki
cf246d5166
ACPI: Add top-level ASL
...
Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com >
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-by: Christian Walter <christian.walter@9elements.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-27 15:35:13 +00:00
Zheng Bao
bdd5031ad2
soc/amd/common: Only set write_acpi_tables if ACPI table is enabled
...
In ./include/device/device.h, the struct device_operations is defined
as below.
------------------------------------
#if CONFIG(HAVE_ACPI_TABLES)
unsigned long (*write_acpi_tables)(const struct device *dev,
unsigned long start, struct acpi_rsdp *rsdp);
void (*acpi_fill_ssdt)(const struct device *dev);
void (*acpi_inject_dsdt)(const struct device *dev);
const char *(*acpi_name)(const struct device *dev);
/* Returns the optional _HID (Hardware ID) */
const char *(*acpi_hid)(const struct device *dev);
#endif
------------------------------------
So we also need to add the same #if in the C source.
Change-Id: I488eceacb260ebe091495cdc3448c931cc4a1ae3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-01-27 15:24:58 +00:00
Kyösti Mälkki
3f2467032e
sb,soc/amd: Rename PMOD to PICM in ASL
...
Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-27 11:19:38 +00:00
chenzanxi
6dc6ee6e72
mb/google/dedede/var/sasukette: Generate SPD ID for supported memory parts
...
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
K4U6E3S4AA-MGCR
BUG=None
TEST=Build the sasukette board.
Change-Id: I57c9d22ae655032120f19add98ef454853428af5
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2021-01-27 10:25:16 +00:00
Kyösti Mälkki
4abc731831
ACPI: Separate device_nvs_t
...
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-01-27 10:25:03 +00:00
Martin Roth
aeffa86cc5
src/device: Don't die() on vBIOS errors
...
Systems can boot to the OS without a display. Don't kill the boot
process based on a vBIOS error, instead just display a warning.
If the issue is actually fatal for some reason, it's going to die
at some point anyway.
BUG=b:175843172
TEST=Boot morphius to OS without a display
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org >
Change-Id: I7d261321cdbe423dd754f6a354e5f50b53563fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-01-27 10:24:44 +00:00
Marshall Dawson
656743fb6b
soc/amd/common: Notify SMU of AC/DC state upon resume
...
As a result of S3 resume, call ALIB function 1 to report the current
AC/DC state.
BUG=177377069
TEST=Verify printf is called during resume on Morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: I3e52b0625c1222f10ea27568d5431328131a26a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-27 10:24:36 +00:00
Angel Pons
022c62a7a4
mb/clevo: Drop redundant select HAVE_SMI_HANDLER
...
Already selected from SoC Kconfig.
Change-Id: I131f435ab0a30e33a70773a99c60284f8b9c82c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2021-01-27 10:24:32 +00:00
Felix Held
68a1cb58c0
soc/amd/common/block/smbus: remove stale comment
...
The comment doesn't apply to Stoneyridge, Picasso and Cezanne which are
the only SoCs selecting SOC_AMD_COMMON_BLOCK_SMBUS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I9024de9d3731a0bc64365f959142bf657a53e193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2021-01-27 00:29:01 +00:00
Elyes HAOUAS
4d088699f8
mb/kontron/ktqm77: Convert to ASL 2.0 syntax
...
Change-Id: I7ba4625075fd3c27092d854903baf140521c8f7b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 21:04:09 +00:00
Elyes HAOUAS
4c77a8b3ed
mb/asus/a88xm-e: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' files are identical.
Change-Id: I8887b869e9ed809f7861b810c2fb994fa2ee062e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 21:00:09 +00:00
Elyes HAOUAS
19a0923ca9
mb/asus/f2a85-m: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' are identical.
Change-Id: I3a5ef0987f2e03e07f1de2b3b10d65dde3827c70
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 21:00:00 +00:00
Elyes HAOUAS
76eaab0fd9
mb/asus/am1i-a: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' are identical.
Change-Id: I856494c634c8c932faa7840b0fd0a35663f4de57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46157
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 20:59:51 +00:00
Elyes HAOUAS
e404eb2aba
mb/bap/ode_e20XX: Convert to ASL 2.0 syntax
...
Change-Id: I07705aed2f41cd0d2a7f4b980046995f44395f07
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:59:23 +00:00
Elyes HAOUAS
ef7ea6b77f
mb/asus/p2b: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' files are identical.
Change-Id: Ib07e4147f7f1b90f721be147d48ed12ae793c4fd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46159
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 20:58:49 +00:00
Elyes HAOUAS
78b05575bf
mb/lenovo/t60: Convert *.asl to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' files are identical.
Change-Id: Iea2c0600d696f9da6774affdc33d9c50d5cf2c95
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:57:23 +00:00
Elyes HAOUAS
0200143db6
mb/kontron/986lcd-m: Convert *.asl to ASL 2.0 syntax
...
Change-Id: I2ef51c0348e76cb34e118ed207de88cc753f8fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:56:53 +00:00
Elyes HAOUAS
a12c15907f
mb/gigabyte/ga-945gcm-s2l: Convert *.asl to ASL 2.0 syntax
...
Generated 'Build/dsdt.dsl' are identical.
Change-Id: Ic01ca9b58fe948fe5ffbc9e80ea4bae91fb6d581
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:56:36 +00:00
Elyes HAOUAS
d70c560a19
mb/msi/ms7721: Convert to ASL 2.0 syntax
...
Generated build/dsdt.dsl files are same.
Change-Id: Iaf26af76935dc8cd9642f047e833f0e8b14e6931
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 20:56:16 +00:00
Elyes HAOUAS
53dd00a6b0
mb/roda/rk9: Convert to ASL 2.0 syntax
...
Generated build/dsdt.dsl are identical.
Change-Id: I3cfa9d3a199a33ac8faddf4dbc1eed0df8703835
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:55:41 +00:00
Elyes HAOUAS
f3985488ff
mb/roda/rv11: Convert to ASL 2.0 syntax
...
Generated build/dsdt.dsl files are identical.
Change-Id: Id12c20dbe949c4badfe07578c6d202cd4cfb8191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46211
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 20:54:31 +00:00
Elyes HAOUAS
24130ec42c
mb/google/stout: Convert to ASL 2.0 syntax
...
Generated 'build/dsdt.dsl' files are identical.
Change-Id: I1ceb2abdd2562c145b01db7307d817c858d6b978
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:54:08 +00:00
Elyes HAOUAS
6c78420bcb
soc/intel/braswell/romstage/romstage.c: Use __func__
...
Change-Id: I07d36fb9b499e64eaba8829073c040792a2fee6e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:52:35 +00:00
Elyes HAOUAS
f984aecc02
device/pci_device.c: Use __func__
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Change-Id: Ia6c7de99164682dcbcc375969403d2bfb9675f3c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-26 20:52:10 +00:00
Angel Pons
aded1d7fd0
arch/x86/car.ld: Fix up blob reserved regions
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Drop duplicated assignment that rewound `.` back, and broke platforms
using MRC.bin and DCACHE_RAM_MRC_VAR_SIZE.
Tested on out-of-tree Acer E5-573 (Broadwell), fixes booting.
Also tested on Asrock B85M Pro4 (Haswell), also fixes booting.
Change-Id: I3f0153f776c07acf7cf92808b677b118c60507c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49909
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 18:01:16 +00:00
Angel Pons
aaa4a0d39e
cpu/intel/common/fsb.c: Add Broadwell CPUID models
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Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for
both the traditional and ULT variants of Broadwell, because the CPU
driver for Haswell already contains CPUIDs for both Broadwell types.
Without this patch, Broadwell CPUs would hang when trying to print the
first console log message, but only if flashconsole was not enabled.
This was missed in commit f542b7bcefth3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 17:29:20 +00:00
Zheng Bao
64d0ad347b
soc/amd: Add an option to select if SOC supports ESPI sub decode
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Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.
Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-26 15:51:36 +00:00
Eric Lai
56868b8045
mb/google/brya: Add memory DQ map
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Add memory DQ map based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: I94102240b13d2b95e0295f41bc2c0ba078faf242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48446
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 10:38:49 +00:00
Felix Held
3ebfd3fb1c
mb/google/zork/Kconfig.name: remove double space in board variant names
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: If0bc153cd3a3391b1607848436f0ab5fcd54ce7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-26 10:37:27 +00:00
Johnny Lin
38cb7c1615
mb/ocp/deltalake: Replace space with underscore in Locator string
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Per Facebook BIOS requirements 'Locator' field should not
have any space between words.
Tested=On OCP Delta Lake, dmidecode -t 17 to verify.
Change-Id: I2f6f1b2590c55d6da4ca32aef2f50eb332f441dc
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-26 10:37:10 +00:00
David Wu
1f7a39eaf6
mb/google/volteer/var/voema: Add camera ACPI configuration
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Add camera ACPI configuration for Voema
BUG=b:169551066
TEST=Build and boot Voema. Start camera app and able to
capture images.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: I903e5e0b5f85718c7c9cbb6d5cafb8fc9ad5814e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Jim Lai <jim.lai@intel.com >
2021-01-26 10:36:49 +00:00
Marc Jones
05a480acea
ocp/deltalake: Set C-State config
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Set the supported C-State to C1 and C6. This matches the states in
CPUID(5).
Change-Id: If32b8256097b5b2bee7fb074fab105e4b54d14b3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49803
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 10:35:04 +00:00
Marc Jones
31ed8856f9
soc/intel/xeon_sp/acpi.c: Add ACPI C-State table
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Add the soc ACPI _CST table.
The table may be customized to support the different state
combinations and set by the mainboard config.
Tested on deltalake with acpi_idle driver.
Note, intel_idle may not use ACPI _CST table.
Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com >
2021-01-26 10:34:56 +00:00
Marc Jones
08de06ad6d
soc/intel: Move c-state resource define
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De-duplicate the MWAIT_RES define. Move it to intel/common/block.
Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 10:34:52 +00:00
Kyösti Mälkki
3c18186e76
sb,soc/intel: Refactor power_on_after_fail option
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It's only necessary to call get_option() with SLP_TYP S5.
Change-Id: Ic821b429a58a2c0713ec338904364ec57bfbcfce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49251
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 09:14:27 +00:00
Kyösti Mälkki
22236a580d
cpu/x86/smm: Remove unused APMC for C-state and P-state
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Change-Id: I7a3a1b63c0ef14b1e24ecce2df66f7970e5eb669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-26 09:14:15 +00:00
Kyösti Mälkki
9e591c409a
soc/amd: Refactor some ACPI S3 calls
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Do not pass ACPI S3 state as a parameter, by locally
calling acpi_is_wakeup_s3() compiler has better chance
for optimizing HAVE_ACPI_RESUME=n case.
Test for acpi_s3_allowed() is already included in the
implementation of acpi_is_wakeup_s3() and is removed
as redunandant.
For ramstage, acpi_is_wakeup_s3() evaluates to
romstage_handoff_if_resume().
Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-26 00:17:38 +00:00
