I also add myself as the Maintainer for the SiFive boards, since I
happen to have both of them and I also ported the HiFive Unmatched to
coreboot.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic0b8e1053c9f5007e29e997c1ff21ff4a496aea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83697
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add GOOGLE FATCAT MAINBOARDS section for src/mb/google/fatcat and
update the maintainers list to add Subrata Banik and Pranava Y N
as maintainers
Change-Id: I5ae0f0d24d43e91c2097c68446bb64b9ae507e2e
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
I am the one who takes care of end to end DPTF (Thermal Management)
related coreboot things across various X86 based platforms.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I08a1ae48bd5b66ee2f7903615e64d0bab5e0d7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
All of the Dell Latitudes from GM45 and until at least Haswell use a
derivative of the MEC5035 EC, and I have been actively working on
coreboot support for this EC and boards that use it. Rename the "E6400
MAINBOARD" section to "DELL LATITUDE" and add mb/dell/snb_ivb_latitude
and mb/dell/e7240 as additional paths.
Change-Id: I7ba46980bfc8569a85593e415f01cc83fe7d67d7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83008
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.
This board has two socketed DIP-8 SPI flash chips and a physical switch
to choose which one should the system boot from. As long as one of them
contains a bootable firmware image, it is possible to reflash the other
chip using the internal programmer by flipping the switch after booting
to OS. Even if one somehow manages to flash unbootable firmware to both
chips, they are socketed: one can carefully remove them from the socket
and reflash them externally, which is a relatively safe procedure (when
compared to in-circuit flashing, especially if the board isn't designed
to safely be flashed in-circuit). In short, the board is hard to brick.
Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH
found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs
so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe
it's something about RcvEn, but it's unlikely it can easily be fixed.
Working:
- All four DIMM slots
- Broadwell MRC.bin for raminit purposes
- Serial port to emit spam
- POST code display
- S3 suspend/resume
- All rear USB 3.0 ports
- Internal USB 2.0 port
- Audio output (green jack)
- Integrated graphics (libgfxinit)
- HDMI
- VBT
- Intel GbE (I218-V PHY and PCH MAC)
- Realtek RTL8111E GbE
- At least one SATA port
- M2_1 slot (Gen3 x4, bifurcated from CPU)
- Flashing internally with flashrom
- SeaBIOS (current version) to boot Arch Linux
- NCT6791D Super I/O software-based fan control
tested using `sensors` and `pwmconfig`, all 6
fan tachometers and 5 PWM outputs work fine.
Untested for now (i.e. should work, will eventually test):
- DVI-I, DisplayPort
- EHCI debug
- Front USB 2.0 and 3.0 ports
- The other audio jacks (as well as SPDIF)
- The other PCIe and M.2 ports
- Non-Linux OSes
- PS/2 combo port (can only test with a keyboard)
Untestable (i.e. cannot test due to unavailable hardware):
- Thunderbolt AIC (Add-In Card) support
Not working:
- Broadwell CPUs, they require more magic to work (working on it).
- Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were
not tested. It seems that the problem is with the controllers.
- Super I/O automatic fan control: not yet implemented in coreboot.
To control fans, use software fan control methods in the meantime.
- Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor,
connected to the board's HDMI output says "Unsupported resolution"
after libgfxinit configured the iGPU outputs in linear framebuffer
mode. HDMI output works fine after Linux's i915 driver takes over.
Not sure if it's specific to the monitor: the HDMI cable is beaten
up, and it is hard to replace (need to relocate the logic board so
that the ports are accessible).
Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It makes little sense to keep these around. Boards maintained on a
branch should use that branch's MAINTAINERS file instead, I'd say.
Change-Id: I670df889ffce82ee4ee4e2b91fe70f18adfcfdfa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
I am the one who takes care of most coreboot things for this board.
Change-Id: I1f587822d60d2f69f34f272685cad50149faf79b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Both boards are most certainly `Supported`, and have been for a long
time. I have no idea why they were labelled as `Maintained` instead.
Change-Id: I02a5979f094b507e9f7d758daf47eeb95064cf0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82221
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When soc/amd/genoa was renamed to soc/amd/genoa_poc and mb/amd/onyx
was renamed to mb/amd/onyx_poc, the MAINTAINERS file wasn't updated, so
no reviewers were added automatically to patches on Gerrit that change
things in soc/amd/genoa_poc or mb/amd/onyx_poc. Fix this by updating the
folder names in the MAINTAINERS file too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib52781ebc98bd2ce9df495526cfaf9d884aace50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81679
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
jacz@semihalf.com is no longer available, czapiga@google.com should be
used instead.
Change-Id: I228b34c961ccf1546103f105276a75409825a432
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79438
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I didn't have enough time, so it's reasonable to remove myself.
Change-Id: I8f7d87f70916f3d0697b6c38ca6d75f3375bd374
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The AMD team is large enough to handle it on their own :)
Change-Id: I58bc265d9ecfdcb8904f32fbc917877211b7f658
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
I don't get around to do proper full reviews of SIO patches since maybe
3 years, so I better remove myself from the maintainers list for that
part of the coreboot tree. If anyone else wants to take this over,
please go ahead. I can still help with some advice and general ideas in
that area, but even the "odd fixes" status that I downgraded the
maintenance status of that sub-tree to some time ago was a bit too
optimistic.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic56b710ffe68c6e407786d551cafac698e8bb61d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77063
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cannon Lake, which covers Coffee Lake and Comet Lake, has been missing
from the maintainers file. Most unmerged patches for it have recently
been abandoned after 2+ years of inactivity.
Change-Id: Ic381f8efc4a423dca83c36605002aeeabf4bfdd9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This includes mb/dell/e6400 and ec/dell/mec5035, the latter being
the EC on the E6400. Also link to my repo containing research
and documentation I wrote for the MEC5035.
Change-Id: I5b521e6b1fce5b076be6f0392d99aafac35b0084
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Now that the next generation of APUs is officially announced, we can
unmask morgana.
The chip formerly known as Morgana is actually Phoenix.
Surprise!
This patch just changes the name across the entire codebase.
Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the following people as maintainers for the cross toolchain.
* Martin Roth
* Felix Singer
* Elyes Haouas
Change-Id: I3fad10baa0f0177693e009a4bbc218c6064611b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
- X86 architecture is maintained, so mark it as such.
- Legacy AMD chips are supported for odd fixes.
- Remove maintainers whose emails are bouncing.
- Remove maintainers who don't have +2 rights in gerrit.
- According to the instructions, we should use S: Orphan, not Orphaned.
- Update incorrect email addresses.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6d47a8c34482c81ff96dbeec760852cba01dabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
- Presumably all of the ec/google subdirectory is maintained
- Add list of Orphan ECs
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia93e8da9898903ae92873a07fb0af2a2aa76e8b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
- AMD reference boards are maintained at least for odd fixes.
- Google panther has become a variant of Beltino, so remove it.
- Remove people whose email addresses are bouncing email.
- Remove people who responded to my email about being a maintainer and
asked to be removed.
- Alphabetize list
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic6ecaae77df2f2edaf724160bce04c038cbd115e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
