Eric Lai
586be058f4
lib/spd: Demote log about using default DDR4 params to NOTICE
...
Demote log level from error to notice. People should aware the SPD
decode might be wrong if it's not the support type.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Change-Id: I55f0968b78baaa2fc9a6bbebf6712fb8bfd349f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kangheui Won <khwon@chromium.org >
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-05-16 04:34:59 +00:00
Elyes Haouas
2e96e9441d
sb/amd/agesa/hudson/hudson.c: Use BIT() macros
...
Also, code reformatting to reduce coding style difference.
Change-Id: I488050a6ab852520734b16032af9a683a3ad1a46
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:58:36 +00:00
Elyes Haouas
e37806766f
sb/amd/*/*/acpi: Reduce stylistic differences
...
Change-Id: I1375b1d18113000b31266030fd7115e23d7cce5f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:57:51 +00:00
Elyes Haouas
9ca1ef96ae
payloads/coreinfo/coreboot_module.c: Remove 'break' after 'return'
...
Change-Id: Icb60115349ef7c4c35635021784138d45c5a8872
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61954
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-16 02:56:31 +00:00
Elyes HAOUAS
dd75aaf3f5
northbridge/intel/i945: Convert to ASL 2.0
...
Change-Id: Iea9630ce7e5bfcc9d1c8699a81bd1c61a0705de8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:55:28 +00:00
Elyes Haouas
90e4d744cc
amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h: Correct SPD_PERSONALITY_BYTE
...
Regarding Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules
DDR3 - Document Release 6 (JEDEC Standard No. 21-C Page 4.1.2.11 – 69)
memory buffer personality bytes is located at bytes 102 ~ 116.
Change-Id: I7d225fb5e80b537b4c0ce1c23b7a4524e9109a7b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:53:59 +00:00
Elyes Haouas
ae2c045733
payloads/nvramcui/nvramcui.c: Reformat code
...
Change-Id: If5b4ae7d9f9046e56ca098c0469b503130bc8707
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:49:50 +00:00
Elyes Haouas
3fd719755d
cpu/amd: Remove unused <cpu/x86/pae.h>
...
Found using:
diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/)
Change-Id: I4cab4b66c3d123dbb8a948a5596aa4975b31139b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:41:33 +00:00
Elyes Haouas
adec3861be
soc/intel/apollolake/romstage.c: Remove unused <cpu/x86/pae.h>
...
Found using:
diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/)
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Change-Id: If0f69fa8fe4a336b4e4d2a148d1e7a911af3c2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:40:55 +00:00
Elyes Haouas
db735c478e
src: Remove unused <cf9_reset.h>
...
Found using:
diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<"
Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:40:14 +00:00
Elyes Haouas
a618e11f1a
mb/{google,ocp}: Remove unused <bootstate.h>
...
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Change-Id: Id4550842a31f89e7eb6c1543512794eeb5e24937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:39:32 +00:00
Elyes HAOUAS
a1009da902
soc/intel: Remove unused <cpu/intel/common/common.h>
...
Change-Id: I25d112941db8214a7e450de5fb512ef8c2c5f5e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:38:57 +00:00
Elyes HAOUAS
910a63ce0d
soc/intel: Remove unused <cpu/x86/tsc.h>
...
Change-Id: I322a94186b92033fc27ba97785b55df09aa317f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:37:00 +00:00
Elyes Haouas
386e8494bb
mb/google/stout: Use pci_update_config32()
...
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Change-Id: Ie1d2965b384e5653958f7f8503c62b8a16fa7bc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:35:10 +00:00
Elyes Haouas
c9b219804b
mainboard/amd/padmelon: Use pci_or_config32()
...
Change-Id: I8d55fc93f6ec413d0cbcea2f8e0a90a76f1803cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:29:58 +00:00
Elyes Haouas
14c49e3646
util/lint/checkpatch.pl: Fix "uninitialized value" error message
...
Change-Id: I74807f240779060158c6769f63a6e9438a6e5fbe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:28:44 +00:00
Elyes Haouas
0014bce46b
util/lint/checkpatch.pl: Fix "Invalid color mode" error message
...
Remove duplicated code:
"if ($color =~ /^[01]$/) {
$color = !$color;
} elsif ($color =~ /^always$/i) {
$color = 1;
} elsif ($color =~ /^never$/i) {
$color = 0;
} elsif ($color =~ /^auto$/i) {
$color = (-t STDOUT);
} else {
die "$P: Invalid color mode: $color\n";
}"
Change-Id: I5713c364edea806e58df26c3a37b4bba7603ed0a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@tutanota.com >
2022-05-16 02:28:02 +00:00
Arthur Heymans
026978bce5
soc/intel/alderlake: Move array declaration
...
Clang does not like array declarations inside plain switch cases. There
are 2 options to fix this: use a block inside the switch statement, or
declare it outside the switch statement. This does the latter.
Change-Id: I9a02136fd63ac171b2bec4647c30c7eece930246
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-05-15 23:58:14 +00:00
Arthur Heymans
7e0af339ee
soc/intel/apl: Drop cbfs bootblock
...
The bootblock is loaded from IFWI so there is no need to have it in
cbfs.
Also remove the FIT handling as that is also handled by the IFWI.
TESTED: up/squared still boots
Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63225
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-15 18:49:13 +00:00
Arthur Heymans
4cd8f61924
soc/intel/acpi_bert.c: Fix formatted print type for size_t
...
Change-Id: I2b02bcecda2257f191c0d0fc9935b1eb673ab3d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2022-05-14 14:19:35 +00:00
Arthur Heymans
2888c80f26
mb/google/eldrid: Fix use of float
...
Floats are not allowed in coreboot.
As the compiler rounded down the value, do so in the code too as this
is a known good value.
Change-Id: I4e180d4cb8e0e1aa68186bfc1daffdc5c339dc64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2022-05-14 14:19:17 +00:00
Tarun Tuli
ec3c41a6ee
soc/intel/alderlake: Fix Coverity CID 1488814
...
CID 1488814: Uninitialized variables (UNINIT)
Commit c66ea98c66ea98taruntuli@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-05-14 14:09:58 +00:00
Robert Zieba
29bc79fddb
util/amdfwtool: Add amdfwread utility
...
Amdfwtool creates AMD firmware images however there is currently no way
to get information from an existing image. This commit adds amdfwread to
support that functionality. At the moment only reading PSP soft fuse
flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`,
example output: `Soft-fuse:0x400000030000041`.
BUG=b:202397678
TEST=Ran amdfwread and verified that it correctly reads the soft fuse
bits, verified that built AMD FW still boots on DUT
Signed-off-by: Robert Zieba <robertzieba@google.com >
Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rob Barnes <robbarnes@google.com >
2022-05-13 15:51:37 +00:00
David Wu
305086c0f2
mb/google/brya/variants/osiris: Init devicetree for osiris
...
Init basic override devicetree based on schematics
BUG=b:224423318
TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: Ie69957b39b5c299846c64f67fb29207cf858e50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64199
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-13 15:47:23 +00:00
David Wu
f5319efa84
mb/google/brya/variants/osiris: Configure GPIOs according to schematics
...
Update initial gpio configuration for osiris
BUG=b:224423318
TEST=FW_NAME=osiris emerge-brya coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: I014bd7ebf94bf687362f7ee734cadfa83f3bde2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com >
2022-05-13 15:47:11 +00:00
Arthur Heymans
a0595759f6
xcompile,clang: increase the number of bracket-depth for CPP
...
Clang has a limit for the number of nested brackets in CPP.
For soc/intel/common/block/include/intelblocks this is a problem as it
largely exceeds the default limit of 256.
Change-Id: I93038f918e07f735394fc495a8ed7371cc5b1569
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62175
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-13 11:03:16 +00:00
Arthur Heymans
3ff19f8dcd
vendorcode/google/sar.c: Fix formatted print of size_t
...
Change-Id: If765f492befd9d08b5fe9e98c887bcf24ce1a7db
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-05-13 11:03:07 +00:00
Arthur Heymans
54c38e4b88
soc/intel/xeon_sp: Remove set but unused variable
...
Change-Id: I3c8c1787c77ed08942c6550ca556875904be2fa2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64242
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-13 11:02:55 +00:00
Arthur Heymans
4c948d213b
soc/intel/xeon_sp/skx: Use correct formatted print for size_t
...
Change-Id: I2acad0763d19b50c02472dfdd33084acbafe4c84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2022-05-13 11:02:28 +00:00
Arthur Heymans
522c92ed35
mb/google/glados: Fix unused variable
...
Commit f89cb241eearthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-13 11:00:59 +00:00
Arthur Heymans
6f9805e0c7
soc/intel/alderlake: Use correct formatted print for size_t
...
Change-Id: Ifc0374ed49ecefc57dec8e72e73bac031838a9f5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64238
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-13 11:00:50 +00:00
Arthur Heymans
e6d6e7dd12
soc/intel/block/crashlog: Remove unused variable
...
Change-Id: I2f89d11c163f56163d5c361a3edad14418bf9fa7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-05-13 11:00:44 +00:00
Arthur Heymans
55f116ac0a
nb/intel/snb/raminit_mrc.c: Remove set but unused variable
...
Change-Id: I1cf656b404b0e880c061b273ef259ca40a6d499a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-05-13 11:00:33 +00:00
Arthur Heymans
990ef56d1b
soc/intel/denverton_ns: Remove always false statement
...
This fixes building with clang.
Change-Id: I7405f031298a35589e435e888af911d916662d23
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63069
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-13 11:00:21 +00:00
Arthur Heymans
10c43d8c37
soc/intel/tigerlake/meminit.c: Fix clang static asserts
...
Clang does not like static asserts on integral constant expressions.
Change-Id: If5890a357ed95153d8ae2efa727c111b05bc6455
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-05-13 11:00:05 +00:00
Arthur Heymans
3473d16640
drivers/intel/fsp1_1: Use C over CPP
...
This fixes building with clang.
Change-Id: Ida464d9ff96af3ff485682fbbf904bb2253ec44f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-05-13 10:59:50 +00:00
Arthur Heymans
25a0c67e9d
Kconfig: Have CONFIG_ASAN depend on COMPILER_GCC
...
-fsanitize=kernel-address is not implemented in clang
Change-Id: Ib8660bf99b940ff9eac7461f5946df0891dd3a4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-05-13 10:59:37 +00:00
Arthur Heymans
98435ed07a
nb/intel/gm45: Enable 64bit support
...
This patch does the following:
- Allow selecting 64bit from Kconfig
- Fix up integer to pointer conversion that gcc complains about
- Add a buildtest target in configs
Tested on Thinkpad X200: boots fine to the payload
Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-05-13 10:57:41 +00:00
Arthur Heymans
cc0b4527a6
nb/intel/gm45/iommu.c: Fix clearing GTT
...
This was dead code as it was checking for the wrong bit (bit 11
indicates the use of shadow GTT). It was doing it at the wrong place
regardless as no BARs are set up.
Move the code clearing GTT into the GMA .init code and do it
unconditionally: if the GTT does not match 2M then the cycles are
simply not decoded.
Tested on thinkpad X200.
Change-Id: Iac3264d484e66e9ca4b3cd3df90ad87a476e31ce
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2022-05-13 10:57:28 +00:00
Arthur Heymans
0cc56a2848
nb/intel/gm45/dsdt: Fix number of PCI busses
...
Linux complained that the numbers in DSDT (256) don't match with the
values in MMCONF (64).
Change-Id: I2ccac64934e8d284e68945f86ec46cb2bf896277
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2022-05-13 10:57:03 +00:00
Arthur Heymans
022d235a1e
nb/intel/gm45: Allow for PCI BARs above 4G
...
Linux needs to know that allocating BARs above 4G is fine so reserve a
region in ACPI for that.
Tested on thinkpad X200: a PCIe window gets allocated above 4G and
Linux does not relocate it.
Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2022-05-13 10:56:42 +00:00
Ian Feng
7066f1575e
mb/google/skyrim: allow MKBP devices and disable TBMC device
...
Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.
BUG=b:230682161
TEST=manual test on Skyrim:
Volume Up/Down and Power buttons, Tablet Mode switch
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com >
Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Jon Murphy <jpmurphy@google.com >
2022-05-12 19:45:26 +00:00
Tarun Tuli
c66ea98577
soc/intel/alderlake: provide a list of D-states to enter LPM
...
Implement sub-function 1 (Get Device Constraints)
of the Low Power S0 Idle Device-Specific Method (_DSM).
This provides a way in which to describe various devices required
D-states to enter LPM (S0ix). The information can be used to help
in diagnostics and understanding of S0ix entry failure.
Values were derived from Intel document 595644 (rev 0.45) and
the ADL FSP sample ASL.
This implementation adds support for ADL. Other SoC's could be
ported to be included as well. If they aren't, they will default
to the existing behavior of a single hardcoded device to ensure
compatibility with Windows.
TEST=Built and tested on brya by verifying SSDT contents
Change-Id: Ibe46a0583c522a8adf0a015cd3a698f694482437
Signed-off-by: Tarun Tuli <taruntuli@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Lance Zhao
2022-05-12 19:44:38 +00:00
Tim Wawrzynczak
da958d679d
mb/google/deltaur: Remove mainboard from tree
...
This board never made it to production, and development on it has long
since stopped; it is a maintenance burden, therefore drop it from the
tree.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2022-05-12 19:41:48 +00:00
Fred Reitberger
35f73bcce1
soc/amd/sabrina/fsp_m_params: fix modification of constant
...
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is
constant. Changing a constant is undefined behavior, so create a local
static instance of usb_phy_config that can be modified safely.
Change-Id: Iedbc49109dcd1da9198fcb2a8f84e2b567cd8f86
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64130
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-12 18:45:04 +00:00
Felix Held
28d012fc4c
vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSP
...
This file started as a copy from Cezanne. Sabrina has less USB ports
than Cezanne. Also the struct definition of fch_usb2_phy has changed and
FSP_USB_STRUCT_MINOR_VERSION is also updated.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2022-05-12 18:44:46 +00:00
Felix Held
3654c779f7
soc/amd/sabrina/fsp_m_params: add defines for FSP USB struct version
...
Add and use defines instead of magic values in fsp_m_params.c. The
values will be updated to match the Sabrina FSP in a follow-up commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64128
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-12 18:44:22 +00:00
Felix Held
68aaa8cc26
soc/amd/sabrina/fsp_m_params: don't hard-code USB PHY config table size
...
Use sizeof instead of having a hard-coded struct length.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I3c39d770a7719e30572e71b6a6c24fa2ad4a9426
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2022-05-12 18:44:11 +00:00
Arthur Heymans
3dc89c5bd7
Makefile.inc: Remove leftover
...
Commit 9a8d0a03dbarthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-05-12 18:42:37 +00:00
Yu-Ping Wu
05f2ff98c6
mb/google/corsola: Enable TPM_GOOGLE_TI50
...
Replace TPM_GOOGLE_CR50 with TPM_GOOGLE_TI50.
BUG=b:232066387
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I0cc787b3104bc47f6f856497bbc0870e0519dc28
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64252
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-05-12 18:42:07 +00:00
