Until recently, there were two options to build edk2, UefiPayloadPkg and
CorebootPayloadPkg. Now, there is only one, UefiPayloadPkg but soon,
there will be Universal Payload.
It makes more sense, as the official edk2 repository doesn't work with
coreboot, to have the build target and repository separate. That will
allow for building either UefiPayloadPkg or Universal Payload from the
official repository, MrChromebox' fork or a custom repository.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If7f12423058ef69838741f384495ca766ccea083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add the `eeprom_read_serial()` function to read serials from the EEPROM.
Note that there's only one buffer now: this means only one serial can be
accessed at the same time, and the buffer needs to be cleared so that it
does not contain old data from other serials. Given that the serials are
copied one at a time into SMBIOS tables, having one shared buffer is not
a problem.
Change-Id: I5c9781e4e599043be756514cfd6dd86dedcf580c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67275
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCH's SGPIO pads are connected to a buffer chip that is powered from
the always-on +3V3_AUX rail. For some cursed reason, when the SGPIO pads
stay configured as SGPIO when a Poseidon system shuts down, voltage from
the +3V3_AUX-powered buffer chip will leak into the +5V rail through the
SATA backplane. Just pulling the SGPIO pads low before the system powers
off stops the +5V rail from being cross-powered.
This issue has only been observed in S5, but it's very likely other
sleep states are affected as well. Thus, always pull the SGPIO pins
low before entering ACPI S3 or deeper because the power supply will
turn off in these states as well.
TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered
after going to S5. We measured 0.17V on our system, but voltages as
high as 0.6V were measured on other systems. Verify that unplugging
the SGPIO cable going to the SATA backplane results in the +5V rail
voltage dropping to 0V, which indicates that the voltage leakage is
exclusively coming from the SGPIO and SATA backplane. Finally, make
sure that the +5V rail voltage drops to 0V after going into ACPI S5
with this patch applied and the SGPIO cable connected.
Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
To be able to change the MAC addresses, it is necessary that the
controllers are in D0 power state. As of FSP MR3, Intel has set the
controllers to D3 power state at the end of FSP-S TSN GbE
initialization. This patch sets the state back to D0 before the
programming of the MAC addresses.
Test:
- Build coreboot with FSP MR4 for mc_ehl2 mainboard
- Boot into Linux and check MAC addr via 'ip a'
Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
apu/amdfw_a was only getting added to CBFS when VBOOT_SLOTS_RW_AB was
selected, but needs to be added in the RW_A only case as well
(VBOOT_SLOTS_RW_A). Since VBOOT_SLOTS_RW_AB selects VBOOT_SLOTS_RW_A,
we can guard amdfw_a and _b separately and both will be added in the
RW_AB case.
TEST=build google/zork with VBOOT_SLOTS_RW_A or VBOOT_SLOTS_RW_AB
selected, ensure amdfw_a and amdfw_b are added to correct CBFS regions
as appropriate.
Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68126
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
apu/amdfw should be restricted to the RO region only when building with
VBOOT + any RW region (RW_A or RW_A + RW_B); it is not tied to ChromeOS
in any way. Fix guarding to match newer AMD platforms (eg, CZN/MDN).
TEST=build google/zork without CHROMEOS, with VBOOT_SLOTS_RW_A
Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68125
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
RaptorLake introduces the support of the Voltage Regulator Fast Vmode
feature. When enabled, it makes the SoC throttle when the current
exceeds the I_TRIP threshold. This threshold should be between
Iccmax.app and Iccmax and take into account the specification of the
Voltage Regulator of the system.
This change provides a mean to:
1. Enable the feature via the `vr_config->enable_fast_vmode'. If no
I_TRIP value is supplied FSPs picks an adapted I_TRIP value for
the current SoC assuming a Voltage Regulator error accuracy of
6.5%.
2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip'
field.
These new fields are considered independent from the other `vr_config'
fields so that the board configuration does not have to unnecessarily
supply other VR settings to enable Fast VMode.
Information about the Fast VMode Feature can be found in the following
Intel documents:
- 627270 ADL and RPL Processor Family Core and Uncore BIOS
Specification
- 724220 RaptorLake Platform Fast V-Mode
- 686872 RaptorLake Lake U P H Platform
BUG=b:243120082
BRANCH=firmware-brya-14505.B
TEST=Read I_TRIP from the Pcode and verify consistency with
a few `enable_fast_vmode' and `fast_vmode_i_trip' settings.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
An optional dGPU can be connected to the second PEG bridge:
-[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
+-01.0-[01]--
+-01.1-[02]----00.0 NVIDIA Corporation GK208M [GeForce GT 730M]
It's possible that the 01.0 bridge is never populated, but we have to
leave it on anyway so 01.1 can be enumerated.
Change-Id: Ieab7a7bf3b31b4ee9d9f12b5d827d866c87356e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Lite Mk IV's can enable fast charging, with support up to 100W
via USB-C PD 3.0.
The default for this is disabled, as it can reduce battery life
span. This patch adds the option to enable fast charging, by
writing 0x01 to 0x18 in the EC space.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie01eb59d3f41b242190973fd9c58b1494320c12a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add variant specific cmos files, which avoid options like "Thunderbolt"
existing in platforms that don't support such options.
This change also removes entries that were never used, including:
* smi_handler
* usb_always_on
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I359e5c5bbf29eb474f2d3bc42a8e80afc0a5d38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
