Remove TODO's for dummy DXIO descriptors, update comment
to reflect what they are. These devices are needed for the
platform to function properly. Also remove the TODO for
DDI descriptors as they are functioning correctly.
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1535c08cac3f0bcb30061aba2aa593eb22109387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This patch contains several minor cleanups related to compiler.h:
- Replace __always_unused() (which is a Linux-specific concept that
doesn't make sense without also having __maybe_unused(), and had zero
uses in the codebase) with __unused() which moves here from helpers.h
- Add __underscores__ to the names of all attributes in the compiler
attribute shorthand macros. This is necessary to make them work in
files where the same name was already used for an identifier (e.g.
cbfstool/cbfs.h's `unused` array of file types).
- Remove libpayload's own copy of compiler.h and make it directly pull
in the commonlib/bsd copy.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9644da594bb69133843c6b7f12ce50b2e45fd24b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This patch ensures the IP initialization being done as part of MTL
bootblock code is able to complete the bootblock phase without any
visible hang.
The re-ordering in the MTL bootblock SoC programming is required to
ensure the SA early initialization is taking place prior to
performing any PCI Read/Write operation (like P2SB bar enabling for
IOE die etc.).
Additionally, Fast SPI init takes place prior to enabling ROM caching
etc.
BUG=b:224325352
TEST= Able to build and start booting the MTL simics.
Without this change, the code execution is stuck as below:
[NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG] IGD: device id ffff (rev ff) is Unknown
[INFO ] PMC: Using default GPE route.
[INFO ] VBNV: CMOS invalid, restoring from flash
[ERROR] init_vbnv: failed to locate NVRAM
[EMERG] Cannot locate primary CBFS
Able to detect the Flash and reading the SPI flash layout in proper
with this change as below:
[NOTE ] coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG] CPU: Intel(R) Core(TM) i7 CPU (server) @ 2.00GHz
[DEBUG] CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG] CPU: AES supported, TXT supported, VT supported
[DEBUG] MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG] PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG] IGD: device id ffff (rev ff) is Unknown
[INFO ] PMC: Using default GPE route.
[INFO ] VBNV: CMOS invalid, restoring from flash
[DEBUG] FMAP: Found "FLASH" version 1.1 at 0x1804000.
[DEBUG] FMAP: base = 0x0 size = 0x2000000 #areas = 33
[DEBUG] FMAP: area RW_NVRAM found @ 112b000 (24576 bytes)
[INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Base code is based of Intel Alder Lake SOC code.
List of changes:
1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
vol1 #621483, vol2 #640858
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The Nvidia GPU kernel driver supports another _DSM subfunction which
is known as NVPCF (Nvidia Platform and Control Framework). The
subfunction informs the kernel driver about Dynamic Boost parameters,
which is done at init time, but can also be changed dynamically.
BUG=b:214581372
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use the common code to save data for fast boot or S3 resume.
An notable improvement that comes with this, is that the same 4K page
is not rewritten all the time. This prolongs the hardware's life.
TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.
Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44295
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Save the regular boot MTRRs that are restored on the S3 path during
the CPU init in cbmem instead of storing them to the SPI flash.
This was probably done because historically this code run with late
cbmem init (in ramstage).
TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.
Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44294
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The size of the data used is fixed in this function so there is no
need for this aritmetic.
The function signature will be changed in a followup commit.
The cache_disable call is dropped as all the codepaths calling the
restore_mtrr function do this already.
TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine.
Change-Id: I3c6df8951d39695cddd4635360d6407d4d001b0a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44293
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
As far as I know the Chromium OS team is the only user of this script,
so align its output with that of other tools used there:
- Replace "Original-Commit-Id" with "GitOrigin-RevId"
- Reuse Change-Id instead of moving it to the Original- prefix, which
leads to the creation of a new Change ID.
Change-Id: I8c39c512901c83a64f00aa48a539e6621f827242
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This allows for some runtime checks on all SMM elements and removes
the need for manual checks.
We can drop completely separate codepaths on SMM_TSEG & SMM_ASEG as the
only difference is where permanent handler gets placed.
TESTED on prodrive/hermes and qemu with SSM_ASEG with 4 cores & SMM_TSEG
with 128 cores. This code figured out quite some problems with
overlapping regions so I think this is the right approach.
Change-Id: Ib7e2e3ae16c223ecfd8d5bce6ff6c17c53496925
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63602
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch removes the MTL CNVi DIDs macros from IA common code and is
added into the generic wifi driver.
As per Intel Connectivity Platform BIOS Guide, Connectivity Controller
IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`.
Previously Garfield Peak DIDs for Alder Lake SoC also added similarly
to generic wifi drivers.
BUG=b:224325352
TEST=Able to build and boot on MTL emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib98762749c71f63df3e8d03be910539469359c68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
- Move EC send/receive polling code to their own functions
- Add named constants for poll timeouts and delay interval
- Use human-readable timeout values
- Add `send`/`recv` functions which support custom timeouts
- Remove extra 10us delays between polling and performing a given
transaction
- Use constants from `ec.h` for standard EC command opcodes
Tested on a Lenovo Edge E530, which takes similar code paths to
the Lenovo Twist S230u.
Change-Id: Ifda5c030ff81f1046be58aa1fcafdcf71a27cd41
Signed-off-by: Abel Briggs <abelbriggs1@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
To simplify the calling sequence for mtk_wdt_preinit() and we always
adjust request setting in mtk_wdt_preinit(), we rename
mtk_wdt_preinit() to mtk_wdt_set_req() and call it in mtk_wdt_init().
From this modification, we can also enable thermal hardware reset
feature (CB:64676, CB:64675) in MT8192 and MT8195.
BUG=none
TEST=build pass
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
gpio_configure_pad function gets called for most of the GPIO
configuration for all the boards. This function is not handling NULL
pointers properly which can cause exception in CPU.
This patch fixes the handling and function is able to return early
in case the NULL pointer is passed or any subsequent child function
calls return NULL.
BUG=None
BRANCH=None
TEST=Compilation works fine for all Alder Lake boards.
Change-Id: I97fad72cdd92f70c7c5e6fdd23fbecf535a6e388
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch configures external V1p05/Vnn/VnnSx rails for Craask
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:233717182
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Since of moving RAPL disabling to common code a config switch is
available to select that RAPL disabling has to be done via MCHBAR.
This patch selects the switch for EHL.
Test: Boot mc_ehl1 and ensure that relevant bits in MCHBAR are the same
as before the patch.
Change-Id: I1d0b7f650aa3ccf89c5c35d9b60a83a1ce48c74f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
In order to enable the UFS controller (PCI device 12.7), the PCI
specification says that the device at function 0 in the same slot must
also be enabled, which is the ISH. Therefore, enable ISH when UFS is
present.
For more context on why this is necessary, see CB:62662 which enabled
UFS and ISH for adlrvp_n.
BUG=b:234136500
TEST=Build test. Will test that UFS works once we have hardware.
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Daniil Lunev <dlunev@chromium.org>
This patch brings the feature of disabling RAPL to common code. It
replaces the current solution for APL and EHL.
For special case if RAPL disabling is only working via changes in MCHBAR
a new config switch was introduced.
Test: Boot mc_apl4/5 with this patch and ensure that the
relevant bits in MSR 0x610 are the same as before the
patch.
Change-Id: I2098ddcd2f19e3ebd87ef00c544e1427674f5e84
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Builds were suddenly failing when the release was done, because the
coreboot version was overflowing a 64 character limit. We don't need
or use the full hash in other places, so limit the hash to just what's
needed to identify the commit.
Change-Id: I57c535ca251792cae2c9a9c951e6b44bb61e4e78
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
